The popular chipset connectivity solutions are UART, SPI and I2C. The oldest and
popular chipset connectivity solution is UART. However, UART is a asynchronous
interface and it does not support data rate beyond 5Mbps. Secondly,we have SPI
interface . The main advantage of SPI interface is,it is a synchronous interface and it
can support communication speed upto 20Mbps. However, there is no uniform spec-
ifcation of SPI, because of that there are multiple differences among SPI enabled
devices. The multiple differences may include different word size,different handshake
methodologies and different commands. The third chipset connectivity solution is
I2C.I2C has the minimum number of logic signals and is the easiest to use among all
chip set connectivity solutions. However,due to minimum number of data lines, the
performance of I2C interface is less and it can support upto 3.4Mbps speed.
To overcome all these shortcomings persisting with popular UART, SPI and I2C
communication interface, a new chipset connectivity solution has been developed for
high speed data communication in IoT applications.
SDIO interface can support data rate upto 200Mbps. For the mobile and consumer
electronics devices like WiFi, SDHC cards, High performance RF modules this per-
formance capability is very important.
The following picture Figure shows the speed comparison supported by different existing communication protocols.
SDIO Host Controller Architecture :-
SDIO Protocol Overview :-
SDIO bus transfers information serially through the bi-directional CMD and DATA pins. Each command packet consists of 48 bits of information on the CMD pin. The command packet includes the command index, argument and CRC check bits. Command is always sent by the host and the response is sent by the SDIO device, also through the CMD pin. Most response packets are also 48-bits long. The host is always the command initiator and the device is always the command target. Not all commands have associated data transfer. Only read and write commands are accompanied by data transfer. The unit of data packet is called a block. Different block size can be defined by the host. Most data block size is 512 bytes. Data can be transferred using either 1 or all 4 data pins. Each data packet is followed by 16 bits of CRC data. SD command processing is heavily state dependent. The device is always in a particular operating state at a given time. Only certain commands are valid in a given state. The host, through the initialization command sequence, changes the device’s operating state until it is ready to transfer data. Command and data transfer are synchronized with a clock signal generated by the host. Initially after reset, the host uses the lowest clock rate of 400 KHz to communicate with the SDIO device. Internal registers in the device/card provide information related to the device’s capability to the host. By knowing the maximum operating frequency, data bus width and other capability information, the host increases the clock rate for optimal performance.
The architecture of SDIO Host Controller can be divided into two parts:-
(A) Command Path Control
(B) Data Path Control
(A) Command Path Control : -
The command path circuit is used to program a command/response sequence. When enabled, the command path shifts out the command index and argument on the CMD_outpin. After the last payload bit is sent, a CRC7 is computed and sent on the bus before generating the end bit. When a response is expected, the command path is configured to CMD_in and waits for the device response.
Command Path State Machine :-
The transmission and reception of commands is controlled by the command path state machine (CPSM). When no command or response is in progress, the command path is in Idle state. When the CPSM is enabled to send a command, the command path moves to Send state until the last bit of the command is sent, then depending on whether a response is expected or not, the CPSM can return to Idle state when no response is expected or move to Wait state, and wait for a start bit on a command pin (start of the response transmission). When a response start bit is detected within the allocated time period, the CPSM moves to Receive state. After receiving the last bit of the response, the CPSM verifies the response’s integrity using the received CRC, and then returns to Idle state. The CPSM returns to Idle state after a timeout if a response start is not detected.
SDIO Command Format : -
The SDIO controller offers high flexibility for configuring the command indexes and arguments. With a flexible 32-bit register for configuring arguments and an independent 6-bit field for the command index, this architecture ensures that the firmware can address any type of card. The command path state machine is able to generate all command tokens, with no restrictions on command index nor argument. In addition, the start bit, transmitter bit, CRC and end bit fields are automatically generated and sent on the bus.
(B) Data-path Control :-
The data path transfers data both to and from the SDIO device. On each SCLK clock cycle, the data path can send one, four or eight bits depending on the bus width configuration. Transfer logic is clocked by the SCLK clock. It is divided into two sub units, one for data sent and one for data received with a dedicated control bit and status flags. The data buffer is not part of the data path. Transmit and receive FIFO logic are mapped in the APB domain. All signals from the different sub units are re-synchronized. The CRC calculator guarantees data integrity between the SDIO device and host. At the end of the data packet, the CRC is calculated automatically.
Data-path State Machine :-
The data path state machine (DPSM) controls the transmission and reception of all data. When the DPSM is in Idle state, the first transition is triggered when the DPSM enable bit and transfer direction are set. For data transmission, when enabled, the DPSM moves from Idle to Wait_S and then to Send state. While in the Wait_S state, the DPSM waits until the data FIFO empty flag is de-asserted.When data is available in the FIFO buffer, the DPSM moves to the Send state.
In Send state, the DPSM starts sending data to a card according to the bus width set in the control register. At the end of data packet, the DPSM sends an internally generated CRC code and end bit, and moves to the Busy state. In Busy state, the DPSM waits for the CRC status flag. If it receives a positive CRC status, it moves to Wait_S state if the SDMMC_D0 pin is not low (meaning that the card is not busy). From Wait_S state, a new packet transmission can start or the DPSM can return to Idle state when all the data is transmitted. A negative CRC status from the card or a FIFO underrun error can force the DPSM to return to Idle state. For data reception, the DPSM moves from Idle to Wait_R state. When a start bit is detected on the bus, the DPSM moves to Receive state, where it remains until a full packet is received. As long as the end of data transfer flag and errors are not detected, the DPSM will keep switching between Wait_R and Receive states. If an error or the end of data transfer flag is detected, the DPSM will return to Idle state. A Read Wait state is an SDIO-specific operation to stall the transfer in order to execute other commands or internal operations. It can be reached from Receive state while a transmission is ongoing or from Idle state. When the firmware requests a read wait stop operation, the DPSM moves to Wait_R state and waits for a start bit from the SDIO device.
Note: This article only describes the SDIO Host Controller Micro-architecture. For more details and HDL Code , please reach out to dhakagyan1@gmail.com
For different command and data sequence , please refer the SD Specification here
-----------------------------------------Thank You-----------------------------------------
Reference : www.sdcard.org
I welcome your feedback, suggestions and corrections if any. Happy Learning !!!
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