Here are some of the important interview questions on Verilog HDL which are frequently asked during interview in Semiconductor industry.
1) What are the different Data Types in Verilog HDL ?
Ans: There are two groups of data types in Verilog , namely Physical and Abstract.
Physical Data Type: -
.Net ( wire, wand, wor, tri, triand, trior ). Default value is Z. Used mainly in structural modelling.
.Register(reg). Default value is x. Used in Dataflow/RTL and behavioral modelling.
Charge Storage Node(trireg). Default value is x. Used in Gate level ans switch level modelling.
Abstract Data Types: - Used only in Behavioral Modelling and Test Fixture.
Integer(integer) - stores 32 bit signed quantity
Time(time) - stores 64 bit unsigned quantity from system task $time.
Real(real) - stores floating point quantity.
Parameter(parameter) - substitutes constant.
Event(event) - is only name reference - does not hold value.
2) Explain the different Structured Procedures in Verilog HDL?
Ans: There are two structured procedures statements , namely initial and always. They are the basic statements for behavioral modelling from which other behavioral statements are declared. They can not be nested, but many of them can be declared within a module.
'initial' Statement - it executes exactly once and becomes inactive upon exhaustion. If there are multiple initial statements , they all start to execute concurrently at time 0.
'always' statement - it continuously repeats itself throughout the simulation. If there are multiple always statements , they all start to execute concurrently at time 0. always statements may be triggered by events using an event recognizing list @ ().
3) What is the difference between wire and reg and when to use each of them ?
Ans:
'wire' Elements ( Combinational Logic) - wire elements are simple wires ( or buses of arbitrary widths). The following are syntax rules when using wires.
wire elements are used to connect input and output ports of a module instantiation together with some other element in your design.
wire elements must be driven by something and can not store a value without being driven.
wire elements can not be used as the left-hand side of an = or <= sign in an always @ block.
wire elements are the only legal type on the left- hand side of an assign statement.
wire elements are the stateless way of connecting two pieces is a Verilog based design.
wire elements can only be used to model combinational logic.
Legal uses of the wire Element-
wire A, B, C, D, E;
wire [8:0] wide;
reg I;
assign A = B & C; // wire with an assign statement
always @ (B or C) begin
I = B | C; // wire on RHS of an always @ assignment
myModule mymodule_instance( .In (D) , .out(E)); // wire as the output of module instantiation
'reg' Elements ( Combinational and Sequential Logic) - reg are similar to wire but can be used to store information ( 'state' ) like registers. Following are the syntax rules when using reg elements.
reg elements can be connected to the input port of a module instantiation.
reg elements can NOT be connected to the output port of module instantiation.
reg elements can be used as outputs within an actual module declaration.
reg elements can NOT be used as inputs within an actual module declaration.
reg is only the legal type on the left-hand side of an always @ block = or <= sign.
reg is the only legal type in the left-hand side of an initial block = sign ( used in Test Benches).
reg can not be used in left-hand side of an assign statement.
reg can be used to create registers when used in conjunction with always @ (posedge clock) blocks.
Legal uses of reg Element -
wire A, B;
reg I, J , k;
reg [8:0] wide;
always @ ( A or B) begin
I = A | B; // reg as LHS of an always @ assignment
end
initial begin // using reg in initial block
J = 1'b1;
#1;
J = 1'b0;
end
always @ ( posedge clock) begin
K <= I; // reg to create a positive- edge triggered register
end
4) When 'wire' and 'reg' Elements are Interchangeable ?
Ans: In below situation they can be interchanged.
Both can appear in the right-hand side of assign statement and always@ block = or <= sign.
Both can be connected to the input ports of the module instantiation.
5) Explain the different Assignments in Verilog HDL ?
Ans: There are three types of Assignment statements in Verilog HDL namely , Continuous , Procedural and Quasi-Continuous Assignments.
Continuous Assignment - These assignments are always active - Changes in RHS expression is assigned to its LHS net.
assign #delay net = expression ; // inertial delay
Procedural Assignment - LHS must be a scalar or vector of registers , and assignment must be performed inside procedure statements (initial or always). Assignment is only active (evaluated and loaded) when control is transferred to it.
There are two types of procedural assignments - Blocking and Non-blocking
Quasi-Continuous (Procedural Continuous ) Assignment - The LHS must be a scalar or vector of registers , and the assignment must be inside procedural statements.
Similar to procedural assignments , however quasi-continuous assignments becomes active and stays active from the point of the assignment until it is deactivated through deassignment. When active, quasi-continuous assignment overrides any procedural assignment to the registers.
begin
...
assign register = expression1; // Activate quasi-continuous
...
register = expression2; // No effect , overridden by active quasi-continuous
...
assign register = expression3; // Becomes active and overrides previous quasi-continuous
...
deassign register; // Disable quasi-continuous
...
register = expression4; //Executed
...
end
Note: There is no delay associated with quasi-continuous assignment. Only the activation may be delayed. However, once it is activated , any changes in the expression will be assigned to the register immediately.
6) What is meant by inferring latches in design and how to avoid it?
Ans: Inferring latch means to reproduce last value when unknown branch is specified OR A latch is inferred within a combinatorial block where the net is not assigned to a known value. Assign a net to itself will still infer a latch. Latches can also be inferred by missing signals form a sensitivity list and feedback loops.
Ways latches are accidentally inferred -
Signal(s) missing for the sensitivity list (this is why @* should be used)-
always @(a or b) // inferred latch :: "c" missing for the sensitivity list.
begin
out = a + b + c;
end
Missing Condition -
(A)
always @*
begin
case(in[1:0])
2'b00: out = 1'b0;
2'b01: out = 1'b1;
2'b10: out = 1'b1;
// inferred latch "out" :: missing condition 2'b11/default
endcase
end
(B)
always @*
begin
next0 = flop0;
next1 = flop1;
// inferred latch "next2" :: missing initial condition
next3 = flop3;
case(a[2:0])
3'b001: next0 = in;
3'b010: if(b) next1 = in;
3'b100: if(c) next2 = in;
default: if(!b&&!c) next3 = in;
endcase
end
Feedback Loop -
assign out = en ? in : out; // inferred latch "out" :: feedback to mux
assign a = en ? z : c;
// ... any amount of code between ...
assign z = en ? a : y; // inferred latch "a" :: feedback chain
7) How to mitigate the risk of unintended latches in the design?
Ans:
All combinatorial logic blocks need to be defined with always @* or SystemVerilog's always_comb.
Make sure all variables assigned in a combinatorial logic blocks have an initial or default assignment.
-> case statements should have a default condition.
-> if statements should have a corresponding else.
-> When the combinatorial logic blocks is assigning many variables, giving each variable an initial value at the start of the block (before any case or if).
Know where the inputs are coming from and where the outputs are going to.
-> The inputs of combinatorial logic should be flops or the outputs combinatorial logic should be flops.
8) What is the difference between == and === operator?
Ans:
-> Output of == can be 0,1,X while output of === is always 0 or 1.
-> == doesn't compare X and if at least one bit is X output will be X. === compare X bits and output is always 0 or 1 accordingly.
-> === tests 4-state logical equality (tests for 1, 0, z and x) , == tests logical equality (tests for 1 and 0, all other will result in x)
Example : A = 3'b1x0, B = 3'b10x
A == B -> Will give x as output
A === B -> Will give 0 as output
-> '==' is used for comparison of only 1's and 0's. It can't compare X's. If any bit of input is x, output will be X.
-> '===' is used for comparison of X also.
9) Write a Verilog code for synchronous and asynchronous reset?
Ans :
(A)
always @(poseedge clk) //synchronous reset is clock dependent
begin
If (reset)
...
else
...
end
(B)
always @(posedge clock or posedge reset) //Asynchronous reset is clock
//independent
begin
if(reset)
...
else
...
end
10) What is the difference between blocking and Non-blocking assignment ?
Ans:
In Blocking assignment the whole statement is executed before Control passes to next statement, while in non-blocking all the RHS part of the statements evaluates at current time unit and assign to LHS at the end of the time unit
Blocking assignment uses '=' operator whereas non - blocking assignment uses '<=' operator.
11) What are different types of compiler directives in Verilog HDL?
Ans:
There are four types of compiler directives in Verilog -
a. `define b. `include c. `ifdef d. `timescale
a) `define is used to define text macros
For example:-
`define SIZE 16
b) `include is used to import entire Verilog file to another file.
For example if want to include monitor.v file into design.v=
//design.v file
`include monitor.v
c) `ifdef directive checks if the macro has been defined or not if defined
It compiles the code that follows otherwise compiler compiles the code following an optional `else directive
Example - `ifdef SIZE
d) `timescale directives specify time unit and time precision of module that follows it.
Syntax - `timescale unit\precision
12) Write a Verilog code to swap contents of two register with and without temporary registers.
Ans:
//with temporary register
always @(posedge clk)
begin
temp = b;
b = a;
temp = a;
end
//without temporary register
always @(posedge clk)
begin
a<=b;b<=a;
end
13) What do we mean by full case and parallel case?
Ans:
A full case is a case statement in which all possible all possible case expression can be matched with case items or case default. If it is possible to find binary expression that doesn't case item the case statement is not full. A parallel case statement is a case statement in which it is possible to match a case expression with one and only one case item if it is possible to find a case expression that would match more than one case item the matching case is called overlapping or non parallel.
14) What is casex and casez statement?
Ans:
These are the types of case statement in which casex represent x and z as don't care while casez represent z as don't care. Don't cares are not allowed in case statement so casex and casez are used.
15) What are different types of delay control in Verilog?
Ans:
a) Regular delay control
b) Intra assignment delay control
c) Zero delay control
Example:-
//Intra assignment delay control
reg a,b,c;
Initial
begin
a=0,b=0;
c= #5 a+b;
/* Takes value of a and b at time 0 evaluates a+b and then waits 5 time units to assign value to c */
waits 5 time units to assign value to c */
waits 5 time units to assign value to c */
waits 5 time units to assign value to c */
end
//Regular delay control
a=0,b=0;
Initial
begin
temp=a+b;
#5 c=temp
/*Evaluates a+b at current time unit and stores it in temprory variable and then assign it to c at 5 time units */
variable and then assign it to c at 5 time units */
variable and then assign it to c at 5 time units */
variable and then assign it to c at 5 time units */
end
//Zero delay control
initial
begin
a=0;
b=0;
end
Intial
begin
#0 a=1; //Zero delay control
#0 b=1;
end
/* In above code a=0,b=0,a=1.b=1 are to be excuted at simulation time zero but a=1 and b=1 are excuted after a=0,b=0 as zero delay control is applied to these statements. */
In above code a=0,b=0,a=1.b=1 are to be excuted at
simulation time zero but a=1 and b=1 are excuted after
a=0,b=0 as zero delay control is applied to these statements. */
In above code a=0,b=0,a=1.b=1 are to be excuted at
simulation time zero but a=1 and b=1 are excuted after
a=0,b=0 as zero delay control is applied to these statements.
*/
16) What is $time in Verilog?
Ans: $time function is invoked to get the current simulation time.A time variable is a special register data type to store simulation time.$time returns 64bit integer value. Example:
time curr_time;
initial
curr_time = $time;
17) What is defparam?
Ans: Parameter values can be overridden by use of defparam keyword at module instance.It can also change the parameter values at different time interval within the module.
Example:-
module hello;
parameter p1 = 0;
initial
$display ("hello p1 = %d",p1);
endmodule
module Top;
defparam c1.p1 = 2,c2.p1 = 3; //Parameter values are overridden in
module Top
hello c1();//module instance of hello
hello c2();
endmodule
18) What is the difference between task and function?
Ans:
Function doesn't contain timing constraints, task can contain timing constraints
Function must have at least one input argument, Task can contain input, output, inout as argument
Function always return single value, Task does not return value but pass multiple values through output or inout ports.
Function can invoke another function but not task, Task can invoke another task or function
Function executes in zero simulation time , Task can have delay elements
19) What is level sensitive timing control in Verilog?
Ans: We know that @ is used for edge sensitive timing control but Verilog also provides level sensitive timing control i.e processor waits for certain expression or condition to be true to execute the statement. This is provided by 'wait' statement.
Syntax -
wait (expression) statement
Here expression is Boolean value i.e true or false. When true statement is executed. When false it waits for expression to become true.
20) What is PLI?
Ans: PLI is programmining language interface.Essentialy it is a mechanism to invoke C function inside Verilog. It extends Verilog capabilities by allowing users to define their own utilities. Designers can write their own system tasks by using PLI routine.Some PLI application include -
a. Application software like calculator or translator can be written using PLI.
b. Can be used to define customized system tasks and routines.
c. PLI can be used for customized output display.
d. It allows users to change internal data structure.
21) What is force and release in Verilog HDL?
Ans: These are the second form of procedural continuous assignment. They are used to force and release certain values to registers or nets. They are not used in design block and only used in stimulus block or testbench. They are active for certain period only.
The below example shows the use of force and release -
module testbench;
//statements
Dff tdff(q,q_bar,d,clk,rst);
initial
begin
#50 force tdff.Q = 1'b1; //Force Q to 1 at time 50
#50 release tdff.Q; //relaese Q at time 100
end
//statements
endmodule
22) What do we mean by full case and parallel case?
Ans: A full case is a case statement in which all possible all possible case expression can be matched with case items or case default. If it is possible to find binary expression that doesn't case item the case statement is not full. A parallel case statement is a case statement in which it is possible to match a case expression with one and only one case item if it is possible to find a case expression that would match more than one case item the matching case is called overlapping or non parallel.
23) What do you mean parallel block in Verilog?
Ans:
In parallel block all statements are executed concurrently (i.e not sequential) They are specified by keyword fork and join. Timing constraints can be provided in parallel block. Example:-
module parallel;
reg a,b,c;
initial
begin
$monitor ("%g,a=%b,b=%b,c=%b",$time,a,b,c);
fork
#1 a=0;
#5 b=1;
#10 c=0;
join
#1 $display ("%g EXIT",$time);
end
endmodule
In the above code a gets 0 after 1 time unit,b after 5 time unit,c after 10 time units ,EXIT after 11 time units
24) What are different type of FSM coding approach in Verilog HDL?
Ans:
There are mainly four ways to write FSM in Verilog -
(A) Using one process where all input decoder, present state and output decoder are combined in one process.
(B) Using two process where all Combinational and Sequential circuits are separated in different process.
(C) Using two process where input decoder and present state are combine and output decoder separated in other process.
(D) Using three process where all three , input decoder ,present state and output decoder are separated in three process.
25) Find out the value of 'x' in below code snippet when $display executes.
always @ (clk)
begin
x = 0;
x <= 1;
&display(x);
end
Ans: x = 0.
Explanation : Verilog scheduling semantics basically imply a four level deep queue for the current simulation time.
-> Active events ( Blocking Statements )
-> Inactive events (#0 delays etc )
-> Non- Blocking assign updates (Non - Blocking statements )
-> Monitor Events ( $display , $monitor etc)
Since the x= 0 is an active events , it is schedule into the first queue . The x <= 1 is an Non - blocking event , so it is placed in third queue.
Finally , the display statement is placed into the fourth queue. Only events in the active queue are completed in this simulation cycle , so the x = 0 happens and then the display shows x = 0 . if we were to look at the value of a in the next simulation cycle , it would show 1 ( When the process block suspends ).
26) What is the difference between below two lines ?
#5 a = b;
a = #5 b;
Ans:
#5 a = b ; Wait 5 time units before doing the action for a = b
a = #5 b ; The value of b is calculated and stored in an internal temp register . After 5 time units , assign this stored value to a.
27) Write a Verolig HDL code to implement bi -directional ports.
Ans:
module bidirectional(oe, clk, input, output, bidirection);
//port declaration
input oe;
input clk;
input [7:0] input;
output [7:0] output;
inout [7:0] bidirection;
reg [7:0] a , b;
assign bidirection = oe? a : 8'hz;
assign output = b;
//always construct
always @ (posedge clk)
begin
b <= bidirection;
a <= input;
end
endmodule
28) Explain Verilog case(1)?
Ans:
wire [3:0] x;
always @ *
begin
case(1'b1)
x[0] : task0;
x[1] : task1;
x[2] : task2
x[3] : task3:
endcase
end
The case statement walks down the list of cases and executes the first one that matches. For example , if the lowest 1 - bit of x is bit 2, then task2 will get executed.
29) What is the difference between - c = foo ? a : b; and if (foo) c = a ; else c = b;
Ans: The Conditional Operator (?) merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get c = 'b1x. On the other hand, if treats X's or Z's as FALSE, so you'd always get c = b.
----------------------------------------------Thank You---------------------------------------------------
References : Verilog HDL
I welcome your feedback, suggestions and corrections if any. Happy Learning!!!
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