VLSI Excellence

  SR Retention Flip-Flop / Latch Let’s begin by reviewing the basic structures: A standard SR Flip-Flop A standard SR Latch Figure 1: S R Flip Flop Figure 2: S R Latch (Refer to Figure 1 and Figure 2 Why Retention is Needed In low-power designs, parts of a circuit may be powered down to save energy. However, during power shut-down: Regular flip-flops and latches lose their stored data This leads to loss of system state To avoid this, we use retention flip-flops/latches , which preserve data across power cycles. What is a Retention Flip-Flop / Latch? A retention version of a flip-flop or latch is a modified circuit that: Stores its current value before power is turned off Restores the same value when power comes back on (Refer to Figure 3 and Figure 4 for modified circuits) Figure 3: Retention Flip Flop Figure 4: Retention Latch How It Works As shown in Figure 3 and Figure 4: 🔻 During Power Shut-Down A Save signal is asserted The current...

  Chief Aspects of Power Management Power shut-off Isolation Retention Corruption handling Multiple voltage domains Level shifters Note: Leakage power reduction is a key focus in low-power design. Power Network Instrumentation The presence of a power network can impact CDC (Clock Domain Crossing). Power domains can be functionally verified through simulation. Synchronous clocks are affected by DVFS (Dynamic Voltage and Frequency Scaling). Power Cells in Design Power cells may or may not be present in RTL (either RTL-instantiated or inserted via UPF): Retention cells Isolation cells Level shifters Power-Aware CDC Analysis Key Objectives Identify power-aware CDC paths Detect power-aware CDC scenarios, such as: Isolation enable violations Combinational logic violations Retention cell save/restore violations Voltage Domain Crossing (VDC) Identify all VDC paths Check for synchronization and violations across voltage domains ...

  🚀 AMBA Protocol Evolution and SoC Design Trends 📌 AMBA Protocol Evolution Following diagram illustrates AMBA evolution of protocols along with the SoC design trends in industry. AMBA Protocol 🔹 AMBA 1 Specification (First version) Defines two buses/interfaces: Advanced System Bus (ASB) Advanced Peripheral Bus (APB) 🔹 AMBA 2 Specification Defines three buses/interfaces: Advanced High-performance Bus (AHB) – widely used on ARM7, ARM9, and ARM Cortex-M designs Advanced System Bus (ASB) Advanced Peripheral Bus (APB2 or APB) 🔹 AMBA 3 Specification Defines four buses/interfaces: Advanced eXtensible Interface (AXI3 or AXI v1.0) – widely used on ARM Cortex-A processors including Cortex-A9 AHB-Lite v1.0 APB3 v1.0 Advanced Trace Bus (ATB v1.0) 🔹 AMBA 4 Specification Defines: AXI Coherency Extensions (ACE) – widely used on the latest ARM Cortex-A processors including Cortex-A7 and Cortex-A15 ACE-Lite AXI4, AXI4-Lite, AXI4-Stream v...

  🚀 AXI vs AHB: Why AXI Can Be Faster — And When It’s Not When designing high-performance SoCs or embedded systems, one often faces the decision of choosing between different bus protocols. Two popular options from the ARM AMBA family are AXI (Advanced eXtensible Interface) and AHB (Advanced High-performance Bus) . Here are two core reasons why AXI may offer better performance than AHB—and just as importantly, when it doesn’t. 1️⃣ Simplex vs Duplex Transfers AXI supports full duplex communication thanks to its completely independent read and write channels . This means a master can issue and complete a read and write transaction in the same clock cycle , potentially offering up to 2× performance compared to AHB, which is simplex and only allows one operation at a time. ✅ When AXI’s Duplex Mode Shines: The slave must support simultaneous read/write , such as a dual-port SRAM . With multiple slaves , the master can read from one slave and write to another in parallel...

1) Is Isolation Needed Between ON and OFF (Standby) Blocks? Typically, isolation is essential between OFF-to-ON blocks. However, in certain situations, implementing isolation from ON-to-OFF domains is also recommended. The isolation strategy between OFF-to-ON domains is commonly referred to as Parking . This approach is particularly important for special signals with multiple loads in the OFF (Standby) domain, such as RESET or CLK signals. It ensures these signals remain stable and do not toggle while the domain is in the OFF state. By preventing unnecessary switching of sequential elements in the OFF domain, this strategy significantly reduces power consumption. 2) What is the Basic Low Power Sequence Followed in Modern VLSI Design? The fundamental sequence for entering and exiting low power modes is as follows: Save outputs of retention registers Activate isolation control signals (enable isolation) Enable clock gating Apply power gating or shut down power to specific blocks Wait for...

Lint Analysis Lint is a static code analysis technique used to review Hardware Description Language (HDL) code against a predefined set of coding rules and best practices. It helps identify potential design issues early in the development cycle, improving code quality, reliability, and maintainability. Why is Lint Important? Detects coding issues and common design mistakes before simulation and synthesis. Identifies potential mismatches between simulation behavior and synthesized hardware. Ensures compliance with industry coding standards such as STARC and other design guidelines. Reduces debugging effort by finding bugs without the need for extensive test vectors. Minimizes simulation cycles, accelerating verification and improving overall productivity. Enhances design quality and lowers the risk of silicon re-spins. Popular Industry Lint Tools Synopsys SpyGlass LEDA Common Issues Detected by Lint Tools Lint tools can automatically identify a wide range of coding problems, including...