VLSI Excellence

  SR Retention Flip-Flop / Latch Let’s begin by reviewing the basic structures: A standard SR Flip-Flop A standard SR Latch Figure 1: S R Flip Flop Figure 2: S R Latch (Refer to Figure 1 and Figure 2 Why Retention is Needed In low-power designs, parts of a circuit may be powered down to save energy. However, during power shut-down: Regular flip-flops and latches lose their stored data This leads to loss of system state To avoid this, we use retention flip-flops/latches , which preserve data across power cycles. What is a Retention Flip-Flop / Latch? A retention version of a flip-flop or latch is a modified circuit that: Stores its current value before power is turned off Restores the same value when power comes back on (Refer to Figure 3 and Figure 4 for modified circuits) Figure 3: Retention Flip Flop Figure 4: Retention Latch How It Works As shown in Figure 3 and Figure 4: 🔻 During Power Shut-Down A Save signal is asserted The current...

  Chief Aspects of Power Management Power shut-off Isolation Retention Corruption handling Multiple voltage domains Level shifters Note: Leakage power reduction is a key focus in low-power design. Power Network Instrumentation The presence of a power network can impact CDC (Clock Domain Crossing). Power domains can be functionally verified through simulation. Synchronous clocks are affected by DVFS (Dynamic Voltage and Frequency Scaling). Power Cells in Design Power cells may or may not be present in RTL (either RTL-instantiated or inserted via UPF): Retention cells Isolation cells Level shifters Power-Aware CDC Analysis Key Objectives Identify power-aware CDC paths Detect power-aware CDC scenarios, such as: Isolation enable violations Combinational logic violations Retention cell save/restore violations Voltage Domain Crossing (VDC) Identify all VDC paths Check for synchronization and violations across voltage domains ...

  🚀 AMBA Protocol Evolution and SoC Design Trends 📌 AMBA Protocol Evolution Following diagram illustrates AMBA evolution of protocols along with the SoC design trends in industry. AMBA Protocol 🔹 AMBA 1 Specification (First version) Defines two buses/interfaces: Advanced System Bus (ASB) Advanced Peripheral Bus (APB) 🔹 AMBA 2 Specification Defines three buses/interfaces: Advanced High-performance Bus (AHB) – widely used on ARM7, ARM9, and ARM Cortex-M designs Advanced System Bus (ASB) Advanced Peripheral Bus (APB2 or APB) 🔹 AMBA 3 Specification Defines four buses/interfaces: Advanced eXtensible Interface (AXI3 or AXI v1.0) – widely used on ARM Cortex-A processors including Cortex-A9 AHB-Lite v1.0 APB3 v1.0 Advanced Trace Bus (ATB v1.0) 🔹 AMBA 4 Specification Defines: AXI Coherency Extensions (ACE) – widely used on the latest ARM Cortex-A processors including Cortex-A7 and Cortex-A15 ACE-Lite AXI4, AXI4-Lite, AXI4-Stream v...

  🚀 AXI vs AHB: Why AXI Can Be Faster — And When It’s Not When designing high-performance SoCs or embedded systems, one often faces the decision of choosing between different bus protocols. Two popular options from the ARM AMBA family are AXI (Advanced eXtensible Interface) and AHB (Advanced High-performance Bus) . Here are two core reasons why AXI may offer better performance than AHB—and just as importantly, when it doesn’t. 1️⃣ Simplex vs Duplex Transfers AXI supports full duplex communication thanks to its completely independent read and write channels . This means a master can issue and complete a read and write transaction in the same clock cycle , potentially offering up to 2× performance compared to AHB, which is simplex and only allows one operation at a time. ✅ When AXI’s Duplex Mode Shines: The slave must support simultaneous read/write , such as a dual-port SRAM . With multiple slaves , the master can read from one slave and write to another in parallel...

1) Do we need any isolation strategy between ON - to - OFF (Standby) Block ? - Generally the isolation is required between OFF - to ON Block but in some cases it is recommended to use isolation between ON - to -OFF domain as well. - Normally the isolation strategy between OFF - to - ON is called as Parking - This kind of strategy is required for some special kind of signals which have multiple loads in the OFF (Standby) domain, for example - RESET/CLK - This is to insure that the RESET/CLK do not toggle when the domain is in OFF state - This prevents switching of many sequential elements in the OFF domain and hence helps in reducing the power consumption 2) What is the basic Low Power Sequence followed in modern VLSI Design ? Below is the basic sequence of Low Power Entry/Exit - Save the retention register outputs - Assert the isolation control signals ( Enable the isolation) - Enable Clock Gating - Apply the Power Gating /Shutdown th...

Lint : - A Static analysis of code (e.g HDL) based on a series of rules and guidelines that reflect good coding practices, common errors that tend to lead to buggy code or problems - Lint tools are used to check potential mismatches between simulation and synthesis in VLSI Design - Lint incorporates syntactical compliance checks against various coding best practice standards such as STARC - Lint can catch bugs without requiring specific test vectors and hence reduces the number of simulation cycles needed to achieve coverage of a logic block - Industry standard Famous LINT Tools : Synopsys SpyGlass, LEDA Typical LINT Targets : - Unintentional Latches (Latch inference) - Unused Declarations - Un-Synthesizable Constructs - Missing Parameters in Hierarchical Modules - Race Conditions - Multiple Driver issue - Undriven Signals ...

In Multi Voltage VLSI Design, isolation cells play an important role in the modern VLSI world. Requirement : Lets have a look at the below diagram - - Lets assume VDDA voltage domain is always ON and VDDB voltage domain can go ON or OFF based on the certain design requirements ( To minimize the power consumption of the whole design) - When VDDB domain is OFF , the outputs of all the gates of this domain are at unpredictable state. - Since , some of the gates of VDDB domain might be driving some logic in VDDA domain (Which is always ON) but since VDDB domain signals are at unknown state (X) and they might corrupt the logic in VDDA domain and eventually the VDDA domain functionality gets corrupted - To avoid such scenario , we need to isolate the signals going from VDDB(OFF) to VDDA(ON) domain by the use of nothing but called as isolation cells - By using isolation cells we will clamp the respective logic to a proper value (0 or 1 or Latch ) Isolation cell...