Hardware Design Interview Question - Qualcomm

1) Why do we have ‘hready’ as an input to the slave device?

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2) What is the issue with below code snippets?

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3) What is the FIFO depth we need to synchronize data between 100MHz (Source) and 25MHz (Destination) domain OR
What is the minimum required FIFO depth to transfer data from a 100 MHz to 25 MHz domain with any data loss?
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4) Design circuits to implement AND, OR , XOR and Latch using 2*1 MUX?

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5) Write Verilog HDL code to implement a F/3 Frequency counter?

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6) Why AXI protocol does not have a ‘hready’ signal?


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7) How will you find a out of range clock signal? How to calculate the phase of a signal?


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8) What are the different types of data synchronizers and their specific application?


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9) What is the issue with below circuit with respect to ‘hold’ timing check?




Note : D0 is +ve Edge FF and D1 is -ve Edge FF

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10) What are combinational loops in a design and how they impact the design adversely?

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11) Explain CDC Convergence and Divergence Problem?

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