Hardware Design Interview Questions - INTEL

1) What is the issue with below code snippets?


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2) How does 2DFF solves unpredictability? (NDFF solves unpredictability and not metastability?)
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2) 3) Is there any issue with below data synchronizer? If yes, how it can be resolved?









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4) Find out the maximum operating frequency for below circuit?









(Hint: Also check if the circuit can operate without any issues?

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5) What is reset synchronizer? Explain with circuit diagrams?

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6) What is the purpose of data whitening?

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7) There is 10:1 frequency ratio for Input and Output clock domain. How to synchronize write pointer, so that we can not lose track of empty condition?Any other option other than req-handshake synchronizer?

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8) Write parity detector for an input stream of data?

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9) How can you fix hazards during sequence transitions? If there is a hazard in a counter circuit when the count value transition from 5 to 6?

(Hint: Detect count values (which creates glitch) and pass through some logic gates to clear the counter for that particular transition which might cause glitch/hazard)

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10) What are the possible LINT issues?

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11) What is Latch inference? How to avoid it?

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