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Design of Serial Peripheral Interface (SPI) Using Verilog HDL
SPI (Serial Peripheral Interface) Design:- SPI is a synchronous serial data link between a master and multiple slave devices. Since clock is...
Data-To-Data [Non-Sequential] Timing Checks
Data To Data Timing Checks : - Setup and hold checks between two data pins (neither of these is defined as a clock) - Also referred as No...
Design of Cyclic Redundancy Code Generator Using Verilog HDL
Cyclic Redundancy Check (CRC) for SDIO Protocol Please visit SDIO Protocol here . However, the described CRC calculation al...
UPF1.0 Basic Syntax Part#1
Here, are the examples of UPF1.0 basic syntax. 1) Create Supply Ports & Supply Nets & Connect Supply Nets create_supply_net VCC...
Verilog HDL Design of a Bi-Directional Pin/Pad
In this blog, we will be going through the circuit design of a bi-directional Pad/Pin. We will also go though its Verilog HDL Design. Lets g...
Digital Design of N - Bit Magnitude Comparator (Circuit + Verilog HDL Code)
N-Bit Magnitude Comparator - N bit magnitude comparators can be created by cascading 1 bit or 2 bit or 4 bit magnitide comparators - In this...
Fundamentals of LINT
Lint : - A Static analysis of code (e.g HDL) based on a series of rules and guidelines that reflect good coding practices, common er...
Digital Design of 4 - Bit Carry Look Ahead Adder ( Circuit + Verilog HDL)
Carry Look-ahead Adder: - A carry look-ahead adder reduces the total propagation delay as compared to a ripple carry adder - Propagation d...
Verilog HDL Examples - Design of Fixed Priority Arbiter
Fixed Priority Arbiter : - Device that takes as input N requests, and outputs a single grant in the form of a one hot - Arbiter circuit i...
Static Timing Analysis - Part#7 (Timing Constraints)
Timing Constraints: - There are two main problems which can arise in synchronous lo...
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Digital Design of Parallel Adder/Subtractor (Circu...
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