There are 2 basic reasons why AXI may be faster:
1) Simplex Vs Duplex Transfers
AXI has completely independent channels for read/write, which enables full duplex mode of data transportation. That is to say read and writes can take place simultaneously, giving 2x boost over AHB in any circumstances. However, this will ONLY be possible when the slave is able to process 1 read and 1 write operation simultaneously in 1 clock cycle. Which in many cases will be possible, e.g. if the slave is a dual port SRAM which can process 1 read and 1 write transaction simultaneously. Also in this example, we are considering 1 Master and 1 Slave. But in case of multiple slaves, the master can send read transaction to 1 slave and write to other slave, even if the slave(s) cannot handle more than 1 transactions in single clock cycle.
To make more clarity, in a system where there is only 1 master and only 1 slave, the slave is unable to process read and write in 1 single clock cycle simultaneously and both master and slave are in single synchronous clock domain with no clock delay between the master and the slave there won’t be any difference in performance between AXI and AHB. The AXI will only consume more power and area.
2) When there are clock cycle delays between a Master and a responding slave.
This is usually when the Master clock and slave clock is Async, and a there is a clock domain crossing bridge.
It can be observed in the diagram shown below, that that as the number of OTs (outstanding transaction) increase in AXI, the efficiency increases. It can also be observed that with 1 OT, again, the performance will be comparable, if we are doing only reads or only writes.
In AXI case, since the system is able to issue outstanding transactions (OT), i.e. able to issue addresses without waiting for data to return, there is only a initial delay, and then the continuous flow of data follows.
In AHB this is not possible. The AHB cannot issue another transaction, without first receiving the response to its only transaction, which it can issue at a time.
It is to be noted again, that if there are no clock delays between a master and a slave, and if we assume only 1 master and 1 slave in the system, then again the AXI performance will be equal to AHB performance, if we are doing only reads or only writes.
AHB Lite Vs AHB:
AHB Lite is a reduced version of AHB protocol. AHB Lite essentially means that there is only 1 master.
This in turn means
1. No Arbitration
2. No HBUSREQ signal, no HGRANT signal
3. No HSEL Signal
4. No Split or Retry response type -> HRESP can only be 1 bit
5. No Early Bus Termination.
How to connect a full AHB Master to AHB Lite Slave
1. Leave the HBUSREQ open
2. Tie the HGRANT to '1'
How to connect a AHBLite Master to full AHB Slave
1. Feedback the HREADY_out from the Slave back into the HREADY_In at slave (A slave will have hready as input and as output) but also connect the HREADY_out from Slave to the Master.
2. Tie the HSEL '1' at the Slave.
AHB Split Transfer-
In a AHB based Interconnect system, where the interconnect is essentially an AHB Bus, the bus is ownedby 1 master at a time, and it is held by the master at least till it completes the ongoing transfer. Now what if a slave is presented by a read command, and the slave is incredibly slow. Say it takesmultiple clock cycles to produce the data it is requested to provide. Now starting from the point of time read transaction is presented to slave, till it ready to produce response, the slave will pull hready low, and will keep the bus engaged. Now the whole system is stalled, and no other master is able to do any operation.
The SPLIT response now comes into picture, and is able to change this scenario.
The AHB protocol allows the slave to issue a SPLIT response to a transaction, thereby relinquishing the bus for the other masters in the system to be able to use the bus. As the slave issues a SPLIT response, it records the master ID (HMASTER) of the transaction and memorizes it.
When this slave is ready to respond to the SPLITted transaction, it informs the arbiter using HSPLIT signal.
HSPLIT has 1 bit for every master, and a '1' in a bit specifies which master this Slave is talking about.
The arbiter would then grant the bus to the SPLITted master on the earliest opportunity, and let it complete the transaction. This improves the overall system performance.
- Improved bus utilization
- May cause deadlocks if not carefully implemented
------------------------------------Happy Learning--------------------------------------
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