Power Aware Clock Domain Crossing

Chief Aspects of Power Management :

· Power Shut-off

· Isolation

· Retention

· Corruption

· Multiple Voltages

· Level shifters

Note: Leakage Power Reduction is Key in Low-Power Design

Power Network Instrumentation -

· Presence of power network may impact CDC

· Power domains may be functionally verified with simulation

· Synchronous clocks are affected by DVFS (Dynamic Voltage and Frequency Scaling)

Power Cells may/may not present in RTL (RTL instantiated V/S UPF inserted) -

· Retention Cells

· Isolation Cells

· Level Shifters

Power Aware CDC Analysis-

· Identify Power Aware CDC paths

· Detect Power Aware CDC scenarios

Ø Isolation enable violation

Ø Combinational logic violation

Ø Retention cell save/restore violation

· Detect Voltage Domain Crossing schemes

Ø Identify all VDC paths

Ø Check for VDC synchronizations & violations

Below are the various examples where Power Aware Design can have multiple Clock Domain Crossing issues reported. Lets have a look at some of such cases -

Example (1) - PA affecting CDC correctness (RTL Paths) :




RTL Paths after DFP(Design-for-Power) Insertion-





· Insertion of isolation cell logic may add new CDC paths

· Implement power control logic

Ø UPF specifies power domain crossings and isolation-enable signals

Example (2) - Isolation Enable Missing Synchronizer :





· Blocks B1&B2 are in clock c1

· Iso_en comes from block B3 in clock domain c2

· New violation for the new CDC path B3->B2

Isolation Enable Missing Synchronizer Fix-




· Solution: Synchronize iso_en from domain c2 to domain c1 before use

Example (3) - Isolation Causes Combo-logic Violation :


· Synchronized CDC path B1->B2 (clock c1 to c2)

· Isolation cell adds combinational path before synchronizer

Example (4) - Retention Cell Causes Missing Synchronizer :






· Retention cell adds paths to save and restore pins

· New CDC violation B1=>B2

Dynamic Frequency and Voltage Scaling(DVFS) :

Frequency and Voltage interdependence

· Max operating frequency dependent on voltage

· Reducing frequency allows voltage & power reduction

"Small voltage reductions = large power savings"

· Power consumption proportional to supply voltage (P α V2 *)



Example (5) - Voltage Domain Crossing :

· Voltage domains create asynchronous clock groups

· Identify crossings between synchronous paths on different voltage domains


· Identify CDC paths that start or end on DVFS voltage domains

· New CDC violation B1=>B2


------------------------------------------Happy Learning----------------------------------------