Design a Circuit for Retention SR Flip-Flop/Latch

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SR Retention Flip-Flop / Latch

Let’s begin by reviewing the basic structures:

  • A standard SR Flip-Flop
  • A standard SR Latch
Figure 1: S R Flip Flop


Figure 2: S R Latch

(Refer to Figure 1 and Figure 2

Why Retention is Needed

In low-power designs, parts of a circuit may be powered down to save energy.
However, during power shut-down:

  • Regular flip-flops and latches lose their stored data
  • This leads to loss of system state

To avoid this, we use retention flip-flops/latches, which preserve data across power cycles.

What is a Retention Flip-Flop / Latch?

A retention version of a flip-flop or latch is a modified circuit that:

  • Stores its current value before power is turned off
  • Restores the same value when power comes back on

(Refer to Figure 3 and Figure 4 for modified circuits)

Figure 3: Retention Flip Flop
Figure 4: Retention Latch








How It Works

As shown in Figure 3 and Figure 4:

🔻 During Power Shut-Down

  • A Save signal is asserted
  • The current output of the flip-flop/latch is captured and stored in a D-latch
  • This D-latch is powered by an always-on supply, so it retains the value

🔺 During Power Restoration

  • A Restore signal is asserted
  • The saved value from the D-latch is fed back
  • The flip-flop/latch is re-initialized to its previous state

Key Takeaway

Retention flip-flops and latches ensure that:

  • Data is not lost during power shut-down
  • System resumes operation from the same state after power-up

Conclusion

Retention cells are an essential part of low-power design, enabling reliable operation across power cycles. They help maintain system state without requiring a full reinitialization.

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