Design a Circuit for Retention SR Flip-Flop/Latch

SR Retention Flip-Flop/Latch : - Lets have a look at a normal SR Flip Flop and Latch as below - Figure#1 : SR Flip-Flop Figure#2 : SR Latch...

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Digital Circuit Design - Problem#5

Problem: Design a digital circuit which can generate a pulse which is high for 16 clock cycles and then goes low (Active High Reset Signal)as shown in the below waveform Solution : - Lets have a look at previous problem where we discussed on how can we generate an active low reset...

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Digital Circuit Design - Problem#4

Problem : Design a digital logic circuit to generate a reset pulse which is low for 16 clock cycles (Active Low Reset Generation) as shown in below waveform. Solution : - Here we need a output signal of the circuit which is low for 16 cycles and then becomes high - Can 16 flop in a cascade manner do...

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Digital Circuit Design - Problem#3

Problem : Design a digital logic circuit to generate a stick bit as shown in the below waveform. The circuit takes an input as I/P and runs at a clock speed of CLK Solution : - Once the input is high the output should always remain high irrespective of whether the I/P signal is toggling at later point...

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Digital Circuit Design - Problem#2

Problem : Design a black box circuit shown below whose input clock and output relationship is shown in below waveform. Solution : - Lets have a look at below circuit diagram - - Now lets see how the waveform looks like for this circuit - ...

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Digital Circuit Design - Problem#1

Problem : Design a digital circuit as depicted in below block diagram which takes DIN as an input and runs at a clock speed of CLK and generates an output DATA as shown in the waveform below.Solution : - Since the circuit sample the data at both positive and negative edge of the clock, we need both...

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Verilog HDL Examples - Design of an Event Detector (Circuit Design)

Problem : Design a circuit which detects and event (for one clock cycle) whenever there is a change (Either rising edge or falling edge)in the input signalSolution : 1) The input signal is asynchronous to the Event Detector logic domain -Note: The data_in must come out of a register from the source...

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Verilog HDL Examples - Design of Gray Code Counter (For FIFO Design)

Gray Code : - Named after Frank Gray- Known as reflected binary code (RBC), - Also known just as reflected binary (RB) or Gray Code - An ordering of the binary numeral system such that two successive values differ in only one bit (binary digit) Decimal(Base 10) Binary...

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