Power Aware Clock Domain Crossing

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Chief Aspects of Power Management

  • Power shut-off
  • Isolation
  • Retention
  • Corruption handling
  • Multiple voltage domains
  • Level shifters

Note: Leakage power reduction is a key focus in low-power design.

Power Network Instrumentation

  • The presence of a power network can impact CDC (Clock Domain Crossing).
  • Power domains can be functionally verified through simulation.
  • Synchronous clocks are affected by DVFS (Dynamic Voltage and Frequency Scaling).

Power Cells in Design

Power cells may or may not be present in RTL (either RTL-instantiated or inserted via UPF):

  • Retention cells
  • Isolation cells
  • Level shifters

Power-Aware CDC Analysis

Key Objectives

  • Identify power-aware CDC paths
  • Detect power-aware CDC scenarios, such as:
    • Isolation enable violations
    • Combinational logic violations
    • Retention cell save/restore violations

Voltage Domain Crossing (VDC)

  • Identify all VDC paths
  • Check for synchronization and violations across voltage domains

Power-Aware Design and CDC Issues

Below are common scenarios where power-aware design introduces CDC issues:

Example 1: Power-Aware (PA) Impact on CDC (RTL Paths)

RTL Paths before DFP(Design-for-Power) Insertion-

    RTL Paths after DFP(Design-for-Power) Insertion-

  • Insertion of isolation logic can introduce new CDC paths
  • Power control logic must be properly implemented
  • UPF defines:
    • Power domain crossings
    • Isolation enable signals

Example 2: Missing Synchronizer for Isolation Enable


  • Blocks B1 and B2 operate on clock c1
  • Signal iso_en originates from block B3 on clock c2
  • This creates a new CDC path: B3 → B2

Fix:

  • Synchronize iso_en from clock domain c2 to c1 before use

Example 3: Isolation Causes Combinational Logic Violation


  • Existing synchronized CDC path: B1 → B2 (c1 → c2)
  • Insertion of an isolation cell introduces a combinational path before the synchronizer
  • This leads to a CDC violation

Example 4: Retention Cell Introduces Missing Synchronizer


  • Retention cells add paths for save and restore signals
  • These new paths can introduce CDC violations (e.g., B1 → B2)

Dynamic Voltage and Frequency Scaling (DVFS)

Key Concepts

  • Maximum operating frequency depends on supply voltage
  • Lowering frequency allows reduction in voltage and power

Small voltage reductions can lead to large power savings

  • Power consumption is proportional to the square of voltage:
    P ∝ V²

Example 5: Voltage Domain Crossing (VDC)


  • Different voltage domains create asynchronous clock groups
  • Important checks:
    • Crossings between synchronous paths in different voltage domains
    • CDC paths starting or ending in DVFS-controlled domains
  • Example violation: B1 → B2

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