VLSI Excellence

Here , we will discuss a digital circuit which can be optimized for low power. Lets see how this circuit may consume higher power and how can we optimize it for the low power consumption. Lets analyze the below circuit - Here, by analyzing the topology of this circuit, we can clearly see that the output of FF#1 and FF#2 is not always concurrently observable by the downstream logic and it is controlled by FF#3. Now, Lets see how can we gate the switching activity of FF#1 and FF#2 when their output is not observable/used by the downstream logic. Lets have a look at the below modified circuit - Here , you see that when FF#1 path is selected for the downstream logic , FF#2 is clock gated and when FF#2 path is selected for the downstream logic, FF#1 is clock gated. Hope this problem gives some insights on how a power optimized efficient circuit can be designed. Please do like/share/comments to reach out these problems to a wider audience !!! Thanks.

Here , we will discuss a Circuit which can be optimized for low power. Lets see how this circuit may consume higher power and how can we optimize it for the low power consumption. Lets analyze the below circuit - Here we see that when the enable is off, the datapath operator (Multiplier and Adder) output is ignored. In this situation, the datapath is consuming power to compute a result that is not used. Well, now we understand the issue with this circuit with respect to power consumption. Lets now analyze how can we avoid this unnecessary switching activities of Datapath Operators when their output is not being used. Lets have a look at the below modified circuit diagram - As you see here, we had put a isolation circuit before the datapath with it's enable signal as 'ENABLE' ( Yes, our original circuit ENABLE signal ) Now, When the datapath result is not being used, the datapath can be kept quiet by isolating it from its inputs with a latch. The power savings are due to l...

Here , we will discuss a Circuit which can be optimized for low power. Lets see how this circuit may consume higher power and how can we optimize it for the low power consumption. Lets Get Started - Below is the circuit. Lets analyze how this circuit consumes more power (Assume, Adder is functional more time and Shifter is functional infrequently) Since the shifter here is used infrequently, is it possible that we can just Gate the data going into it ? and only let the data pass to the shifter when the shifter is functional ? Yes. We can do that !!! But how ? Well, here the shifter data is only used when the 2*1 Mux selects the shifter output data that means when the Mux selection line is HIGH. Can we just use this Mux selection line to Gate the input data of Shifter ? So only when the Mux Selects the shifter output data, the data will be passing into the shifter/processing and available at the input line of Mux. Lets see how the new modified circuit diagram looks like - Below is the...

Here we will discuss a problems which causes unnecessarily higher power consumption and can be easily handled by carefully analyzing the hardware. Problem: 1) As you see in the below figure#1 , the clock is always enabled for the D-FF and even when there is no data available, the clock is always toggling and results in the increased switching power (Also known as Dynamic Power ) {Figure#2} Figure#1 Figure#2 Solution : If we can generate an enable signal such that the clock toggles only when there is an activity on the D input. Lets have a look at figure #3 below Figure#3 Here, the EN signal is 1 only when the...

Introduction:- During Desktop PC design era VLSI design efforts were mainly focused on optimizing speed to realize computationally intensive real time functions such as video compressing , graphics, gaming etc. While these solutions have addressed the real time issues still the increasing demand of portable operations where the mobile needs to pack all these functions without operating much power is unaddressed. The strict limitation on power dissipation in portable electronics applications such as smart phones and tablet computers must be met by the VLSI chip designer while still meeting the computational requirements. Hence, the most important factor while designing SOC for portable devices is "Keep the Power Consumption MINIMUM!!!’ Please download the file below for detailed concepts used for lowering power consumption in SoC Design. Low Power VLSI Design Note - This article and the attached "Low Power VLSI Design" file is under the further improvements and review an...