Verilog HDL Interview Questions
Here are some of the important interview questions on Verilog HDL which are frequently asked during interview in Semiconductor industry. 1) What are the different Data Types in Verilog HDL ? Ans: There are two groups of data types in Verilog , namely Physical and Abstract. Physical Data Type: - .Net ( wire, wand, wor, tri, triand, trior ). Default value is Z. Used mainly in structural modelling. .Register(reg). Default value is x. Used in Dataflow/RTL and behavioral modelling. Charge Storage Node(trireg). Default value is x. Used in Gate level ans switch level modelling. Abstract Data Types: - Used only in Behavioral Modelling and Test Fixture. Integer(integer) - stores 32 bit signed quantity Time(time) - stores 64 bit unsigned quantity from system task $time. Real(real) - stores floating point quantity. Parameter(parameter) - substitutes constant. Event(event) - is only name reference - does not hold value. 2) Explain the different Structured Procedures in Verilog HDL? Ans: There are...