New- AMBA Bus Architecture & Protocol Understanding - Part#3

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🚀 AXI vs AHB: Why AXI Can Be Faster — And When It’s Not

When designing high-performance SoCs or embedded systems, one often faces the decision of choosing between different bus protocols. Two popular options from the ARM AMBA family are AXI (Advanced eXtensible Interface) and AHB (Advanced High-performance Bus).

Here are two core reasons why AXI may offer better performance than AHB—and just as importantly, when it doesn’t.

1️⃣ Simplex vs Duplex Transfers

AXI supports full duplex communication thanks to its completely independent read and write channels. This means a master can issue and complete a read and write transaction in the same clock cycle, potentially offering up to 2× performance compared to AHB, which is simplex and only allows one operation at a time.

✅ When AXI’s Duplex Mode Shines:

  • The slave must support simultaneous read/write, such as a dual-port SRAM.

  • With multiple slaves, the master can read from one slave and write to another in parallel—even if individual slaves can't handle both in a single cycle.

❌ When Duplexing Doesn’t Help:

If the system has:

  • Only one master and one slave

  • The slave cannot perform simultaneous read/write

  • Both operate in a single synchronous clock domain

...then AXI provides no performance advantage over AHB. In fact, AXI might consume more power and silicon area in such cases, without any throughput gain.

2️⃣ Outstanding Transactions (OTs) and Clock Domain Crossing

AXI can issue multiple outstanding transactions—address requests can be queued without waiting for the corresponding data response. This is especially powerful in asynchronous systems with clock domain crossings between master and slave.

In such systems:

  • AXI’s pipelined model allows a continuous flow of data after an initial delay.

  • Throughput improves as the number of outstanding transactions increases.

  • In contrast, AHB can issue only one transaction at a time and must wait for a response before continuing.

🔍 Example:

Imagine a read from a slow slave. In AHB, the entire bus stalls. But with AXI, the master keeps issuing new transactions—maximizing efficiency.

📌 Caveat:

Again, if:

  • The system has only one master and one slave

  • There are no clock domain delays

  • Transactions are only reads or only writes

...then AXI and AHB offer comparable performance, with AXI potentially adding power and area overhead.

🔁 AHB Lite vs Full AHB

AHB Lite is a simplified version of the AHB protocol designed for single-master systems. Key differences include:

❌ Removed in AHB Lite:

  1. No arbitration (only one master)

  2. No HBUSREQ / HGRANT signals

  3. No HSEL (slave select) signal

  4. No split or retry responses (HRESP is only 1-bit)

  5. No early bus termination

🔗 Interfacing Full AHB with AHB Lite

➕ Full AHB Master to AHB Lite Slave:

  • Leave HBUSREQ open

  • Tie HGRANT to '1'

➕ AHB Lite Master to Full AHB Slave:

  • Connect HREADY_out of the slave back to its HREADY_in, and also to the master

  • Tie HSEL high ('1') at the slave

🔄 AHB Split Transfers

In a multi-master AHB system, a slow slave can stall the entire bus by pulling HREADY low during a long response time. This blocks all other masters—a clear performance bottleneck.

💡 Enter SPLIT Transactions:

When a slave anticipates a long delay:

  • It issues a SPLIT response, freeing the bus for other masters.

  • The slave stores the ID of the master (HMASTER) that initiated the request.

  • Once ready, it signals the arbiter via the HSPLIT line (1 bit per master).

  • The arbiter then reassigns the bus to the original master to resume the split transaction.

This approach:

  • ✅ Improves overall bus utilization

  • ⚠️ Requires careful design to avoid deadlocks or starvation

📝 Conclusion

FeatureAXI    AHB     AHB Lite
Full Duplex Support✅    ❌    ❌
Outstanding Transactions✅    ❌        ❌
Clock Domain Crossing Efficiency✅    ❌    ❌
Multiple Masters✅    ✅    ❌
Simplified Interface❌    ❌    ✅
Split Transactions❌    ✅    ❌

AXI is clearly more powerful—but only when your system can take advantage of its features. For simpler use-cases, especially single-master synchronous systems, AHB or even AHB Lite might be more area- and power-efficient.

📚 Happy Learning!

Let me know if you’d like this turned into a downloadable PDF, a LinkedIn post, or a presentation deck!

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