Digital Design of N - Bit Magnitude Comparator (Circuit + Verilog HDL Code)

N-Bit Magnitude Comparator:

- N bit magnitude comparators can be created by cascading 1 bit or 2 bit or 4 bit magnitide comparators

- In this blog we are going to develop N - Bit Magnitude Comparator using 1 - Bit Magnitude Comparators


Block Diagram of N Bit Magnitude Comparator:    

Circuit Diagram of N Bit Magnitude Comparator:

     

Note:

- The AEQB_in of first comparator need to be tied to ONE inorder to perform comparision of first bit in the N bit number

- AGB_in and ALB_in of first comparator can be tied to ZERO


Verilog HDL Code:

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// Code your design here

`include "magnitude_comparator_1_bit_type2.sv"

module magnitude_comparator_n_bit_type2#(parameter N = 4)(a_in, b_in, aeqb_o, agb_o, alb_o, aeqb_in, agb_in, alb_in);

  input [N-1 : 0] a_in;

  input [N-1 : 0] b_in;

  output aeqb_o;

  output agb_o;

  output alb_o;

  input aeqb_in;

  input agb_in;

  input alb_in;

  genvar gen;

  wire [N : 0] aeqb_w;

  wire [N : 0] agb_w;

  wire [N : 0] alb_w;

  assign aeqb_w[0] = aeqb_in;

  assign agb_w[0] = agb_in;

  assign alb_w[0] = alb_in;    

generate 

    for (gen = 0; gen < N; gen++)

      begin        

        magnitude_comparator_1_bit_type2 CMP(.a_in(a_in[gen]), .b_in(b_in[gen]), .aeqb_in(aeqb_w[gen]), .agb_in(agb_w[gen]), .alb_in(alb_w[gen]), .aeqb_o(aeqb_w[gen + 1]), .agb_o(agb_w[gen + 1]), .alb_o(alb_w[gen + 1]));

      end

endgenerate        

  assign aeqb_o = aeqb_w[N];

  assign  agb_o = agb_w[N];

  assign  alb_o = alb_w[N];

endmodule

module magnitude_comparator_1_bit_type2(a_in, b_in, aeqb_o, agb_o, alb_o, aeqb_in, agb_in, alb_in);

  input a_in;

  input b_in;

  output aeqb_o;

  output agb_o;

  output alb_o;

  input aeqb_in;

  input agb_in;

  input alb_in;

  

 /* a_in      b_in    aeqb     agb    alb

    0        0       1        0      0

    0        1       0        0      1

    1        0       0        1      0

    1        1       1        0      0        */  

  

 reg aeqb_w, agb_w, alb_w;

  always @(*)

    begin

      if(aeqb_in)

        begin

          aeqb_w = ((~a_in & ~b_in) | (a_in & b_in));

           agb_w = (a_in & ~b_in);

           alb_w = (~a_in & b_in);

        end

      else

        begin

          aeqb_w = aeqb_in;

           agb_w = agb_in;

           alb_w = alb_in;

        end

    end

 assign aeqb_o = aeqb_w;

 assign agb_o = agb_w;  

 assign alb_o = alb_w;

endmodule

Test Bench Code:

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module magnitude_comparator_n_bit_type2_test;

  parameter N = 4;

  reg [N-1 : 0] a_in;

  reg [N-1 : 0] b_in;

  reg aeqb_in;

  reg agb_in;

  reg alb_in;

  wire aeqb_o;

  wire agb_o;

  wire alb_o;

  // Instantiate design under test

  magnitude_comparator_n_bit_type2 #(4) DUT(.a_in(a_in), .b_in(b_in), .aeqb_in(aeqb_in), .agb_in(agb_in), .alb_in(alb_in), .aeqb_o(aeqb_o), .agb_o(agb_o), .alb_o(alb_o));

  initial begin

    // Dump waves

    $dumpfile("dump.vcd");

    $dumpvars(1);

    a_in = 4'b0;

    b_in = 4'b0;

    aeqb_in = 1'b0;

    agb_in = 1'b0;

    alb_in = 1'b0;

    #10 a_in = 4'b0001; b_in = 4'b0000;

    #10 a_in = 4'b0100; b_in = 4'b1001;

    #10 a_in = 4'b1010; b_in = 4'b1000;

    #10 a_in = 4'b1110; b_in = 4'b0010; 

    #5 aeqb_in = 1'b1;

    #10 a_in = 4'b0001; b_in = 4'b0000;

    #10 a_in = 4'b0100; b_in = 4'b1001;

    #10 a_in = 4'b1010; b_in = 4'b1000;

    #10 a_in = 4'b1110; b_in = 4'b0010; 

  end   

endmodule

Thanks !