Digital Design of 4 - Bit Carry Look Ahead Adder ( Circuit + Verilog HDL)

 

Carry Look-ahead Adder:

- A carry look-ahead adder reduces the total propagation delay as compared to a ripple carry adder

- Propagation delay reduction comes at a cost of more complex hardware to be introduced in Carry Look-ahead Adder

- Trade-off between propagation delay and area between carry look-ahead adder and ripple carry adder

- If speed is the concern ( Need Faster ) - Go for carry look-ahead adder else if area is the concern (Need Less Area ) - Go for Ripple Carry Adder


Block Diagram of Carry Look-ahead Adder:

   

Full Adder Truth Table:

a_in	b_in	carry_in	sum_o	carry_o
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

                                              Table 1 : Full Adder Truth Table

a_in	b_in	carry_in	carry_out	Type of Carry
0	0	0	0	None
0	0	1	0	None
0	1	0	0	None
0	1	1	1	Carry Propagate
1	0	0	0	None
1	0	1	1	Propagate
1	1	0	1	Carry Generate
1	1	1	1	Carry Generate/Propagate

                                             Table 2 : Carry Generate , Carry Propagate

Logic Expression for Carry Generate and Carry Propagate ( From Table 2)

    Carry Genearte (cg) = a_in . b_in;

    Carry Propagate (cp) = a_in' . b_in + a_in . b_in';

    cp = a_in ^ b_in;

In General ,

    cp[i] = a_in[i] ^ b_in[i];

    cg[i] = a_in[i] . b_in[i];

For 4 bit Carry Look-ahead Adder -

    cg[0] = a_in[0] & b_in[0];

    cg[1] = a_in[1] & b_in[1];

    cg[2] = a_in[2] & b_in[2];

    cg[3] = a_in[3] & b_in[3];

    cp[0] = a_in[0] ^ b_in[0];

    cp[1] = a_in[1] ^ b_in[1];

    cp[2] = a_in[2] ^ b_in[2];

    cp[3] = a_in[3] ^ b_in[3];

Now, we know that carry expression for a full adder is -

    carry_out= (a_in ^ b_in)carry_in + a_in . b_in;

In General,

    carry[i + 1] = cp [i] . carry[i] + cg[i];

    Input stage Carry = carry[0];

Output Carry from First Stage ,

    carry[1] = cp[0] . carry[0] + cg[0];

    carry[2] = cp[1] . carry[1] + cg[1];

Putting Value of carry[1] ,

    carry[2] = cp[1] . (cp[0] . carry[0] + cg[0]) + cg[1];

    carry[2] = (cg1 | (cp1 & cg0) | (cp1 & cp0 & carry0));

Similarly,

    carry[3] = (cg[2] | (cp[2] & cg[1]) | (cp[2] & cp[1] & cg[0]) | (cp[2] & cp[1] & cp[0] & carry[0]));

    carry[4] = (cg[3] | (cp[3] & cg[2]) | (cp[3] & cp[2] & cg[1]) | (cp[3] & cp[2] & cp[1] & cg[0]) | (cp[3] & cp[2] & cp[1] & cp[0] & carry[0]));

    

Verilog HDL Code:

--------------------------------------------------------------------------------------------------------------------------

`module carry_look_ahead_adder_4_bit

    
    
module carry_look_ahead_adder_4_bit(a_in, b_in, carry_in, sum_o, carry_o);
  input [3:0]a_in;
  input [3:0]b_in;
  input carry_in;
  output [3:0]sum_o;
  output carry_o;
  wire g0, g1, g2, g3;  // Carry generate
  wire p0, p1, p2, p3;  // Carry Propogate 
  wire c0, c1, c2, c3, c4;      // Next step carry 
  wire c_1, c_2, c_3, c_4;
  assign g0 = a_in[0] & b_in[0]; 
  assign g1 = a_in[1] & b_in[1];
  assign g2 = a_in[2] & b_in[2]; 
  assign g3 = a_in[3] & b_in[3];
  assign p0 = a_in[0] ^ b_in[0];
  assign p1 = a_in[1] ^ b_in[1];
  assign p2 = a_in[2] ^ b_in[2];
  assign p3 = a_in[3] ^ b_in[3];
 // C1 = G0 + P0 · C0
 // C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0
 // C3 = G2 + P2 · C2 = G2 + P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0
 // C4 = G3 + P3 · C3 = G3 + P3 · G2 + P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0
  assign c0 = carry_in;
  assign c1 = (g0 | (p0 & c0));
  assign c2 = (g1 | (p1 & g0) | (p1 & p0 & c0));
  assign c3 = (g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c0));
  assign c4 = (g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) | (p3 & p2 & p1 & p0 & c0));

  full_adder FA1(.a_in(a_in[0]), .b_in(b_in[0]), .carry_in(c0), .sum_o(sum_o[0]), .carry_o(c_1)); 
  full_adder FA2(.a_in(a_in[1]), .b_in(b_in[1]), .carry_in(c1), .sum_o(sum_o[1]), .carry_o(c_2));
  full_adder FA3(.a_in(a_in[2]), .b_in(b_in[2]), .carry_in(c2), .sum_o(sum_o[2]), .carry_o(c_3));
  full_adder FA4(.a_in(a_in[3]), .b_in(b_in[3]), .carry_in(c3), .sum_o(sum_o[3]), .carry_o(c_4));
  assign carry_o = c4;  
endmodule

module full_adder (a_in, b_in, carry_in, sum_o, carry_o);
  input a_in;
  input b_in;
  input carry_in;
  output sum_o;
  output carry_o; 
  assign sum_o = (a_in ^ b_in ^ carry_in);
  assign carry_o = (((a_in ^ b_in)& carry_in) | (a_in & b_in));
  //assign carry_o = ((a_in & b_in) | (b_in & carry_in) | (a_in & carry_in));  
endmodule

  

Test Bench Code:

--------------------------------------------------------------------------------------------------------------------------

module carry_look_ahead_adder_4_bit_test

 
module carry_look_ahead_adder_4_bit_test;
  reg [3:0]a_in;
  reg [3:0]b_in;
  reg carry_in;
  wire [3:0]sum_o;
  wire carry_o;
   
  // Instantiate design under test
  carry_look_ahead_adder_4_bit DUT(.a_in(a_in), .b_in(b_in), .carry_in(carry_in), .sum_o(sum_o), .carry_o(carry_o));
       
  initial begin
    // Dump waves
    $dumpfile("dump.vcd");
    $dumpvars(1);
    
    a_in = 4'b0000;
    b_in = 4'b0000;
    carry_in = 1'b0;
    
    #10 a_in = 4'b0000; b_in = 4'b0001; carry_in = 1'b1;   
    
    #10 a_in = 4'b0001; b_in = 4'b0001; carry_in = 1'b0;
    
    #10 a_in = 4'b0010; b_in = 4'b0011; carry_in = 1'b1; 
    
    #10 a_in = 4'b1111; b_in = 4'b1010; carry_in = 1'b0;
    
    #10 a_in = 4'b1001; b_in = 1'b1000; carry_in = 1'b1;
    
    #10 a_in = 4'b1101; b_in = 4'b1001; carry_in = 1'b0; 
    
    #10 a_in = 4'b0001; b_in = 4'b0011; carry_in = 1'b1;
    
    #10 a_in = 4'b0001; b_in = 4'b0000; carry_in = 1'b0;
   
  end 
      
endmodule

Simulation Waveform:

   

Thanks !