Verilog HDL Examples - Design of Fixed Priority Arbiter

Fixed Priority Arbiter :

- Device that takes as input N requests, and outputs a single grant in the form of a one hot

- Arbiter circuit is used to grant access to a shared resource when there are multiple requests to access it

- Example (1) : Accessing a memory location by multiple process

- Example (2): In routers where users are competing for a switch

- The priority of the request signals is fixed in such fixed priority arbiters

- Example : Assume, there are 4 input request signals to the arbiter, the highest priority request will be granted the access to the shared resource. If the highest priority is give to REQ[4] , then GNT[4] will be asserted high even if there are other active requests are present





Verilog HDL Code for Fixed Priority Arbiter:

Assume the priority order is : REQ[3] > REG[2] > REQ[1] > REQ[0]


//---------------------------Fixed Priority Arbiter --------------------------------------------//

module fixed_priority_arbiter(

input clk,

input rst,

input [3:0] REQ,

output [3:0] GNT

);

always @ (posedge clk or negedge rst)

begin

if(!rst)

GNT <= 4'b0000;

elsif(REQ[3])

GNT <= 4'b1000;

elsif(REQ[2])

GNT <= 4'b0100;

elsif(REQ[1])

GNT <= 4'b0010;

elsif(REQ[0])

GNT <= 4'b0001;

else

GNT <= 4'b0000;

end

endmodule

Test Bench:

// Code your testbench here

module fixed_priority_Arbiter_test;
reg clk;
reg rst;
reg [3:0] REQ;
wire [3:0] GNT;

//Instantiate Design Under Test

fixed_priority_arbiter DUT(.clk(clk), .rst(rst), .REQ(REQ), .GNT(GNT));

//Generate a 10 ns Time Period Clock
always #5 clk = ~clk;

//Drive the DUT or Generate stimuli for the DUT

initial begin
clk = 0;
rst = 1;
REQ = 4'b0;
// Assert the Asynchronous Reset after 1 clock period
#10 rst = 0;
//Deassert the Reset
#5 rst = 1;

@(negedge clk) REQ = 4'b1000;

@(negedge clk) REQ = 4'b1010;

@(negedge clk) REQ = 4'b0010;

@(negedge clk) REQ = 4'b0110;

@(negedge clk) REQ = 4'b1110;

@(negedge clk) REQ = 4'b1111;

@(negedge clk) REQ = 4'b0100;

@(negedge clk) REQ = 4'b0010;

#5 rst = 0;

#100 $finish;
end

initial begin
// below two lines are used to show waveform
$dumpfile("dump.vcd");
$dumpvars(1);
end

endmodule

Waveform:




Yosys Synthesis Diagram:





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