Verilog HDL Design of a Bi-Directional Pin/Pad

In this blog, we will be going through the circuit design of a bi-directional Pad/Pin. We will also go though its Verilog HDL Design.

Lets get started -

Below diagram depicts how a bidirectional pad is connected to a VLSI Chip.

                 Figure #1 : Bi Directional Pad Design


The On-Chip Peripheral like QSPI, I2C, SDIO etc Master/Slave Device interacts with an on Platform/Board Peripheral (Master/Slave) through the Chip IO (Input/Output) pins.

The same pad/pin has to work in both input and output direction during the on-going transaction (Example - QSPI bidirectional data lines)

To make this happen, the on-chip peripheral controller (Example - QSPI Slave Controller) has to control the input and output buffers of the IO Cell dynamically during the ongoing transaction.

Click here to know more about QSPI protocol.

Let's now model the above circuit in Verilog HDL.

################# BiDirectionalPad #########################

module BiDirectionalPad(

            input in_en,

            input out_en,

            input d_out,

            output reg d_in,

            inout reg pad

);

always@(*)

        begin

            if(in_en)begin

                    d_in = pad;

            end

            else begin

                    d_in = 1'bz;

            end

            end

always @(*)

        begin

                if(out_en)begin

                    pad = d_out;

                end

                else begin

                    pad = 1'bz;

                end

         end

endmodule


Now let's see how the above code gets synthesized.

Figure #2 : Bi Directional Pad Synthesized RTL View


As expected, we got the same synthesized result similar to our circuit in Figure#1.


Note:

Many industry protocol like QSPI, I2C, SDIO have bidirectional signals. To communicate with a chip through its pad for these signals with their bidirectional nature, the on-chip pad/pin should support the bidirectional functionality.


Thank !