Cyclic Redundancy Check (CRC) for SDIO Protocol
Please visit SDIO Protocol here . However, the described CRC calculation algorithm in this blog is common and the concept can be used anywhere as per the design requirements to generate a 7 bit CRC value over a stream of data.
The Cyclic Redundancy Check (CRC) is intended for protecting SD Card commands, responses and data transfer against transmission errors on the SD Card bus. One CRC is generated for every command and checked for every response on the CMD line. For data blocks, CRC is generated for each DATA line per transferred block. The CRC is generated and checked as described in the following sections:-
The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and CID registers. The CRC7 is a 7-bit value and is computed as follows:
Generator polynomial: G(x) = x7 + x3 + 1.
M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0
CRC [6...0] = Remainder [(M(x) * x7) / G(x)]
The first bit is the most significant bit of the corresponding bit string (of the command, response, CID or CSD). The degree n of the polynomial is the number of CRC protected bits decreased by one. The number of bits to be protected is 40 for commands and responses (n = 39), and 120 for the CSD and CID (n = 119).
Algorithm to implement CRC code:-
This is a general algorithm for generating 8bit CRC code for a string of 8 bit data and can be used to generate any CRC number. The process of CRC calculation using a shift register is as follow:
Initialize the register with 0.
Shift in the input stream bit by bit. If the popped out MSB is a '1', XOR the register value with the generator polynomial.
If all input bits are handled, the CRC shift register contains the CRC value.
Let's visualize the procedure with the example data-
CRC-8 Shift Register Example:-
Input data=0xC2=b11000010 (with 8 zero bits appended: b1100001000000000)
Polynomial=b100011101
1.CRC-8 register initialized with 0. --- --- --- --- --- --- --- ---
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | <-- b1100001000000000
2. Left-Shift register by one position. MSB is 0, so nothing do happen, shift in next byte of input stream. --- --- --- --- ---
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | <-- b100001000000000
3. Repeat those steps. All steps are left out until there is a 1 in the MSB (nothing interesting happens), then the state looks like: --- --- --- --- --- ---
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | <-- b00000000
4. Left-Shift register. MSB 1 pops out: --- --- --- --- --- --- --- ---
1 <- | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | <-- b0000000
So XOR the CRC register (with popped out MSB) b110000100 with polynomial b100011101 = b010011001 = 0x99. The MSB is discarded, so the new CRC register value is 010011001: --- --- --- --- --- --- --- ---
| 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | <-- b0000000
5. Left-Shift register. MSB 1 pops out: b100110010 ^ b100011101 = b000101111 = 0x2F: --- --- --- --- --- --- --- ---
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | <-- b000000
6. Left-shift register until a 1 is in the MSB position: --- --- --- --- --- --- --- ---
| 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | <-- b0000
7. Left-Shift register. MSB 1 pops out: b101111000 ^ b100011101 = b001100101 = 0x65
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | <-- b000
8. Left-shift register until a 1 is in the MSB position: --- --- --- --- --- --- --- ---
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | <-- b00
9. Left-Shift register. MSB 1 pops out: b110010100 ^ b100011101 = b010001001 = 0x89
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | <-- b0
10. Left-Shift register. MSB 1 pops out: b10001001 ^ b100011101 = b000001111 = 0x0F
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | <-- <empty>
All input bits are processed, the algorithm stops. The shift register contains now the CRC value which is 0x0F.
CRC Verification:-
The remainder is the CRC value which is transmitted along with the input data to the receiver. The receiver can either verify the received data by computing the CRC or compare the calculated CRC value with the received one. Or, more commonly used, the CRC value is directly appended to the actual data. Then the receiver computes the CRC over the whole data (input with CRC value appended): If the CRC value is 0, then most likely no bit error occurred during transmission. Let's do verification according the latter case:
Example verification:-
The actual transmission data (input data + CRC) would be b1100001000001111. Note that this is an 8bit CRC, so the actual CRC value is also 8bit long. The generator polynomial is statically defined by the used CRC algorithm and so it's known by the receiver.
1100001000001111
100011101.......
---------.......
010011001.......
100011101.....
---------......
000101111......
100011101..
---------...
001100100...
100011101
---------.
010001110.
100011101
---------
000000000 -> Remainder is 0, data ok!
Experiment Results:-
Figure:-State Machine implementation for CRC Code
A) Top level CRC Generator schematic:-
B) CRC Generator top module internal architecture:-
C) Simulation waveform of CRC Generator:
Note: The implementation project can be found here
--------------------------------------------Happy Learning -------------------------------------------
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