Digital Low Power Design - Problems & Solutions Part#4

Here , we will discuss a digital circuit which can be optimized for low power. Lets see how this circuit may consume higher power and how can we optimize it for the low power consumption.

Lets analyze the below circuit -










Here, by analyzing the topology of this circuit, we can clearly see that the output of FF#1 and FF#2 is not always concurrently observable by the downstream logic and it is controlled by FF#3.

Now, Lets see how can we gate the switching activity of FF#1 and FF#2 when their output is not observable/used by the downstream logic.


Lets have a look at the below modified circuit -








Here , you see that when FF#1 path is selected for the downstream logic , FF#2 is clock gated and when FF#2 path is selected for the downstream logic, FF#1 is clock gated.


Hope this problem gives some insights on how a power optimized efficient circuit can be designed.


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