Digital Low Power Design - Problems & Solutions Part#3

Here , we will discuss a Circuit which can be optimized for low power. Lets see how this circuit may consume higher power and how can we optimize it for the low power consumption.

Lets analyze the below circuit -







Here we see that when the enable is off, the datapath operator (Multiplier and Adder) output is ignored. In this situation, the datapath is consuming power to compute a result that is not used.

Well, now we understand the issue with this circuit with respect to power consumption. Lets now analyze how can we avoid this unnecessary switching activities of Datapath Operators when their output is not being used.

Lets have a look at the below modified circuit diagram -


As you see here, we had put a isolation circuit before the datapath with it's enable signal as 'ENABLE' ( Yes, our original circuit ENABLE signal )



Now, When the datapath result is not being used, the datapath can be kept quiet by isolating it from its inputs with a latch. The power savings are due to lowered activity in the datapath operator.




Trade-offs :

1) Small amount or area/power over-head because of added latching circuitry

2) Added some extra delay in the combinational path, if this datapath is on critical path, this extra delay may not be acceptable.