Digital Low Power Design - Problems & Solutions Part#1

Here we will discuss a problems which causes unnecessarily higher power consumption and can be easily handled by carefully analyzing the hardware.




Problem: 1) As you see in the below figure#1 , the clock is always enabled for the D-FF and even when there is no data available, the clock is always toggling and results in the increased switching power (Also known as Dynamic Power ) {Figure#2}
























Figure#1



Figure#2
Solution : If we can generate an enable signal such that the clock toggles only when there is an activity on the D input. Lets have a look at figure #3 below


Figure#3


Here, the EN signal is 1 only when there is an activity on D input of the flip-flop OR in other words when there is a new data available and for rest of the time clock will be disabled and there would not be any switching power dissipation.


Now, Lets have a look at the HDL side implementation of this problem.
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For example, if the original code for the D-FF implementation is as below:

always @(posedge clk)

q <= d;

You can generate an enable “en” by modifying the code as follows:

en = | (q ^ d);

always @(posedge clk)

if (en)

q <= d;

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Now, Lets discuss a very important point "Trade-offs" of this solution -

· Large Area Impact (As you can see in Figure#3 compared to Figure#1)

· Timing (The levels of logic between the data and the enable can also impact timing. If a change arrives late at the data inputs, it requires some time to propagate into the enable to allow the clock through)

Note :-
 - if a register is only active in one particular mode, there is no reason to build a bus-specific enable—you can simply use the mode control signal as the enable.

 - Carefully selection of the bits upon which to detect changes.