Digital Low Power Design - Problems & Solutions Part#2

Here , we will discuss a Circuit which can be optimized for low power. Lets see how this circuit may consume higher power and how can we optimize it for the low power consumption.

Lets Get Started -

Below is the circuit. Lets analyze how this circuit consumes more power (Assume, Adder is functional more time and Shifter is functional infrequently)







Since the shifter here is used infrequently, is it possible that we can just Gate the data going into it ? and only let the data pass to the shifter when the shifter is functional ?

Yes. We can do that !!! But how ?

Well, here the shifter data is only used when the 2*1 Mux selects the shifter output data that means when the Mux selection line is HIGH.

Can we just use this Mux selection line to Gate the input data of Shifter ? So only when the Mux Selects the shifter output data, the data will be passing into the shifter/processing and available at the input line of Mux.

Lets see how the new modified circuit diagram looks like -

Below is the new modified circuit diagram -





Here the AND Gate will block the data passing into the shifter when the Mux doesn't select it OR when the Mux is processing the Adder Output.

Hence, there will be minimal switching activity inside the Shifter and results in the minimum Power Consumption !!!

Note : You can call this Low Power Technique as "Data Gating" !!!