2) Redundant Logic :
This is an another issue which can occur during RTL coding.
Complex RTL coding styles can hide design redundancies that are not apparent to the naked eyes. Unintentional redundancies may indicate serious functional problems. If these redundancies are not optimized during implementation, they can impact a chip’s quality (timing, area, power). Redundancies are not always local to given block or area of RTL code. Below figure illustrates design redundancy caused by convergence of logic across a sequential layer of flip-flops. Once the clock is active, the signal Data_out can be simplified to a constant 0 since one of the flip-flops q_ff1 or q_ff2 will store the value 0.
Figure #1 : Redundant Logic Driving the Port Data_out
This form of redundant logic is usually caused by branching constructs such as if-then-else and case-statements, which can break the data flow and result in dead code. Designers must ensure the absence of redundant RTL code of the form shown above.
Complex RTL coding styles can hide design redundancies that are not apparent to the naked eyes. Unintentional redundancies may indicate serious functional problems. If these redundancies are not optimized during implementation, they can impact a chip’s quality (timing, area, power). Redundancies are not always local to given block or area of RTL code. Below figure illustrates design redundancy caused by convergence of logic across a sequential layer of flip-flops. Once the clock is active, the signal Data_out can be simplified to a constant 0 since one of the flip-flops q_ff1 or q_ff2 will store the value 0.
Figure #1 : Redundant Logic Driving the Port Data_out
This form of redundant logic is usually caused by branching constructs such as if-then-else and case-statements, which can break the data flow and result in dead code. Designers must ensure the absence of redundant RTL code of the form shown above.
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