Verilog HDL Examples - Blocking V/S Non Blocking Assignment Part#5

Lets understand the Verilog Simulator Scheduling Algorithm.





As you can see in the above diagram, Blocking Assignments are always executed during Active Events of Simulator Scheduling Algorithm.

The RHS part of Non-Blocking assignments is executed during active events but assignment of RHS part to LHS is done during Nonblocking Events.


Observations -

1) All the continuous assignments/procedural blocks executes sequentially (First Come First Execution in the Verilog file)

2) Blocking assignments are executed during Active Event of Verilog Simulator Scheduling

3) RHS part of Non-Blocking assignments executes in Active Event while LHS assignments happens during Non-Blocking Events

Thank !