VLSI Excellence

Isolation Cells in Multi-Voltage VLSI Design As modern VLSI designs focus heavily on reducing power consumption, multiple voltage and power domains are commonly used. In such designs, isolation cells play a critical role in ensuring reliable communication between power domains operating in different states. Why Are Isolation Cells Needed? Consider a design with two voltage domains: VDDA : Always ON VDDB : Can be turned ON or OFF to save power When the VDDB domain is powered down, all logic gates within that domain may produce unknown or unpredictable outputs (X states) . If signals from the powered-down VDDB domain are connected directly to logic in the active VDDA domain, these unknown values can propagate into the always-on circuitry, causing: Functional errors Incorrect logic evaluations Potential corruption of the active domain's operation To prevent this issue, isolation cells are inserted on signals crossing from the OFF domain to the ON domain. What Are Isolation Cells?...

Problem: Design a digital circuit which can generate a pulse which is high for 16 clock cycles and then goes low (Active High Reset Signal)as shown in the below waveform Solution : - Lets have a look at previous problem where we discussed on how can we generate an active low reset pulse which is low for 16 clock cycles - By carefully observing the problem discussed previously and this problem, we can easily identify that the output waveform in both the problems are exactly opposite - If we can add an NOT gate at the output of the circuit discussed previously, we can get the expected waveform for this problem - Lets see the circuit design as below Please like/share and comment if you have any doubts. -----------------------------------------------Happy Learning----------------------------------------

Problem : Design a digital logic circuit to generate a reset pulse which is low for 16 clock cycles (Active Low Reset Generation) as shown in below waveform. Solution : - Here we need a output signal of the circuit which is low for 16 cycles and then becomes high - Can 16 flop in a cascade manner do this job ? - Lets see the below circuit diagram and see if it matches our expectation - - yes, as you see this circuit can generate a pulse which is low for 16 clock cycles and then goes high as the first flip-flop input is tied to '1'. - Assumption here is , initially all the flops are in reset state. ----------------------------------------------------Happy Learning--------------------------------------

Problem : Design a digital logic circuit to generate a stick bit as shown in the below waveform. The circuit takes an input as I/P and runs at a clock speed of CLK Solution : - Once the input is high the output should always remain high irrespective of whether the I/P signal is toggling at later point of time or not - Lets have a look at below circuit diagram and see if it matches our expectation - - As you see here once the input goes high and it is captured properly by the flop , then by the incorporation of an OR gate the D input of the flop will always remain high , provided that reset of the flop is not asserted - Lets try to find the another solution just by writing a HDL pseudo code which translates the problem statement - always@ (psoedge CLK or negedge rstn) if(!rstn) o/p <= 0; else if(i/p) o/p <= 1; else o/p <= o/p; - Lets see how this HDL code can be realized into a hardware - Hope, this problem is helpful in understanding digital logic circuit desi...

Problem : Design a black box circuit shown below whose input clock and output relationship is shown in below waveform. Solution : - Lets have a look at below circuit diagram - - Now lets see how the waveform looks like for this circuit - Key Points : - Negative edge triggered flip -flop alters the output by half clock cycle - Flip-flop can generate an output with the frequency half of its clock frequency ----------------------------------------------------Happy Learning---------------------------------------

Problem : Design a digital circuit as depicted in below block diagram which takes DIN as an input and runs at a clock speed of CLK and generates an output DATA as shown in the waveform below. Solution : - Since the circuit sample the data at both positive and negative edge of the clock, we need both positive edge and negative edge triggered flip-flops - Lets have a look at below diagram - - We notice here that by using both positive and negative edge triggered flip-flops, we are able to sample the DIN at both the clock edges but how will we transfer this sampled data to DATA output port ? - Well, we need to use a 2*1 MUX to select the sampled data from both of the flip-flops but what should be the select signal of this MUX ? - The select signal should be like the CLK signal - Lets have a look at below circuit diagram and see if it can produce a select signal which toggles at CLK frequency - Yes , here the generated SEL signal can be tied to SEL pin of 2*1 MUX and the MUX output...

Problem : Design a circuit which detects and event (for one clock cycle) whenever there is a change (Either rising edge or falling edge)in the input signal Solution : 1) The input signal is asynchronous to the Event Detector logic domain - Note: The data_in must come out of a register from the source domain or the logic for data_in must be generated in such a way that it is spike free otherwise the synchronizer could catch a glitch and can pass it to the detected event_out 2) The input signal is synchronized to the Event Detector logic domain - Note: - When data_in is generated from a different clock domain than 'CLK', a synchronizer (e.g standard 2 -DFF ) is used to synchronize the data_in in the 'CLK' clock domain - The event_out will get delayed by 2 clock cycles in this case Waveform : Please feel free to like/share and comment for any doubts/clarifications regarding Event Detector circuit design. --...