Problem: Design a digital circuit which can generate a pulse which is high for 16 clock cycles and then goes low (Active High Reset Signal)as shown in the below waveform
Solution :
- Lets have a look at previous problem where we discussed on how can we generate an active low reset pulse which is low for 16 clock cycles
- By carefully observing the problem discussed previously and this problem, we can easily identify that the output waveform in both the problems are exactly opposite
- If we can add an NOT gate at the output of the circuit discussed previously, we can get the expected waveform for this problem
- Lets see the circuit design as below
Please like/share and comment if you have any doubts.
-----------------------------------------------Happy Learning----------------------------------------
- Lets have a look at previous problem where we discussed on how can we generate an active low reset pulse which is low for 16 clock cycles
- By carefully observing the problem discussed previously and this problem, we can easily identify that the output waveform in both the problems are exactly opposite
- If we can add an NOT gate at the output of the circuit discussed previously, we can get the expected waveform for this problem
- Lets see the circuit design as below
Please like/share and comment if you have any doubts.
-----------------------------------------------Happy Learning----------------------------------------
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