Digital Circuit Design - Problem#3

Problem : Design a digital logic circuit to generate a stick bit as shown in the below waveform. The circuit takes an input as I/P and runs at a clock speed of CLK



Solution :



- Once the input is high the output should always remain high irrespective of whether the I/P signal is toggling at later point of time or not

- Lets have a look at below circuit diagram and see if it matches our expectation -







- As you see here once the input goes high and it is captured properly by the flop , then by the incorporation of an OR gate the D input of the flop will always remain high , provided that reset of the flop is not asserted


- Lets try to find the another solution just by writing a HDL pseudo code which translates the problem statement -

always@ (psoedge CLK or negedge rstn)

if(!rstn)

o/p <= 0;

else if(i/p)

o/p <= 1;

else

o/p <= o/p;



- Lets see how this HDL code can be realized into a hardware -





Hope, this problem is helpful in understanding digital logic circuit design and can be very helpful during the interviews.


----------------------------------------------------Happy Learning---------------------------------------