Problem : Design a digital logic circuit to generate a reset pulse which is low for 16 clock cycles (Active Low Reset Generation) as shown in below waveform.
Solution :
- Here we need a output signal of the circuit which is low for 16 cycles and then becomes high
- Can 16 flop in a cascade manner do this job ?
- Lets see the below circuit diagram and see if it matches our expectation -
- yes, as you see this circuit can generate a pulse which is low for 16 clock cycles and then goes high as the first flip-flop input is tied to '1'.
- Assumption here is , initially all the flops are in reset state.
----------------------------------------------------Happy Learning--------------------------------------
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