Design a Generic Pipeline/Repeater Hardware Block for Retiming Using Verilog HDL

To break the long paths which violates the STA timing, pipeline registers are added in between such that they meet the required timing. Below is the Verilog HDL implementation of a simple module which can be used to insert the pipeline registers in a generic design,



//-------------------------------------------------------------------------------------------------------------

// Description

// GENERIC Pipeline Module.

// Setting PIPELINE_STAGE = 0 Makes the Module behave as simple wire logic

//---------------------------------------------------------------------------------------------------------------------

//Module Declaration

module generic_pipeline#(

parameter WIDTH = 1,

parameter PIPELINE_STAGE = 1

)(

input i_clk,

input i_rst_n,

input i_en,

input [WIDTH-1:0] i_din,

output [WIDTH-1:0] o_dout

);

//Declarations

reg [(PIPELINE_STAGE+1)*WIDTH-1:0] pipeline;

//Main Body of Code

//The lower WIDTH bits of the pipeline are the input bits

assign pipeline[0+:WIDTH] = i_din;

//If depth/stages is greater than 0, we create a series of PIPELINE_STAGE register

//words, each WIDTH bits wide. Data moves through this pipeline one step

//per clock cycle when enable is high

generate

if(PIPELINE_STAGE>0)

begin:generate_pipeline

always @(posedge i_clk or negedge i_rst_n)

if(!i_rst_n)

pipeline[WIDTH+:(PIPELINE_STAGE*WIDTH)] <= '0;

else

pipeline[WIDTH+:(PIPELINE_STAGE*WIDTH)] <= i_en ? pipeline[0+:(PIPELINE_STAGE*WIDTH)]: pipeline[WIDTH+:(PIPELINE_STAGE*WIDTH)];

end:generate_pipeline

endgenerate

//The output is the last stage of the pipeline

assign o_dout = pipeline[PIPELINE_STAGE*WIDTH+:WIDTH];

endmodule //generic pipeline


Yosys Synthesis Diagram:





Thanks !!