Here, demonstrated different techniques to design Finite State Machines(FSMs) in Digital System Design.
- Three techniques mostly used designing FSMs as below-
1) Using a Single Process to Code Present State, Next State and Output Logic
2) Using Two Process, One to code Present State and Next State logic and another to code Output Logic,
3) Using Three Process each to call Present State, Next State and Output Logic
Moore and Melay FSM Design Block Diagram :
1) FSM Design Technique Using a Single Process:
// Verilog HDL Code
// Type #1 of FSM design using single process where the present state, next state and output logic are coded in a single process
module FSM_TYPE_1_SINGLE_PROCESS (
input clk,
input reset,
input x,
output reg out
);
reg [1:0] state;
parameter s1 = 2'b00;
parameter s2 = 2'b01;
parameter s3 = 2'b10;
parameter s4 = 2'b11;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
state <= s1;
out <= 1'b1;
end
else begin
case (state)
s1: begin
if (x == 1'b1) begin
state <= s2;
out <= 1'b1;
end
else begin
state <= s3;
out <= 1'b1;
end
end
s2: begin
state <= s4;
out <= 1'b0;
end
s3: begin
state <= s4;
out <= 1'b0;
end
s4: begin
state <= s1;
out <= 1'b1;
end
endcase
end
end
endmodule
Note:
A) Single Process for Present, Next and Output Logic
B) Output Logic is Registered
C) Yosys Synthesis Diagram -
D) EDA Playground Project Link : https://www.edaplayground.com/x/uuTK
2) FSM Design Technique Using Two Processes:
// Verilog HDL Code
// Type #2 of FSM design using single two process where the present state, next state are evaluated in one process and output logic are coded in a another process
module FSM_TYPE_2_TWO_PROCESS (
input clk,
input reset,
input x1,
output reg out
);
reg [1:0] state;
parameter s1 = 2'b00;
parameter s2 = 2'b01;
parameter s3 = 2'b10;
parameter s4 = 2'b11;
always @(posedge clk or posedge reset)
begin
if (reset)
state <= s1;
else begin
case (state)
s1: begin
if (x1 == 1'b1)
state <= s2;
else
state <= s3;
end
s2: state <= s4;
s3: state <= s4;
s4: state <= s1;
endcase
end
end
//Second process to evaluate output logic
always @(state) begin
case (state)
s1: out = 1'b1;
s2: out = 1'b1;
s3: out = 1'b0;
s4: out = 1'b0;
endcase
end
endmodule
Note:
A) Two Process, One to code Present State and Next State and another to code Output Logic
B) Output is un-registered
C) Yosys Synthesis Diagram -
D) EDA Playground Project Link : https://www.edaplayground.com/x/F62f
3) FSM Design Technique Using Three Processes:
// Verilog HDL Code
// Type #3 of FSM design using three process where the present state, next state and output logic are coded in separate three processes
module FSM_TYPE_3_THREE_PROCESS (
input clk,
input reset,
input x1,
output reg out
);
reg [1:0] state;
reg [1:0] next_state;
parameter s1 = 2'b00;
parameter s2 = 2'b01;
parameter s3 = 2'b10;
parameter s4 = 2'b11;
// First process to evaluate present state logic
always @(posedge clk or posedge reset)
begin
if (reset)
state <= s1;
else
state <= next_state;
end
// Second process to evaluate next_state logic
always @(state or x1)
begin
case (state)
s1: begin
if (x1 == 1'b1)
next_state = s2;
else
next_state = s3;
end
s2: next_state = s4;
s3: next_state = s4;
s4: next_state = s1;
endcase
end
//Third process to evaluate output logic
always @(state) begin
case (state)
s1: out = 1'b1;
s2: out = 1'b1;
s3: out = 1'b0;
s4: out = 1'b0;
endcase
end
endmodule
Note:
A) Three Process each to code Present State , Next State and Output Logic
B) Output Logic is un-registered
C) Yosys Synthesis Diagram :
D) EDA Playground Project Link : https://www.edaplayground.com/x/S_6Z
Thanks !!!
0 Comments:
Post a Comment