Digital System Design - Combinational Circuit Design & Optimization Part#1

Topics to be covered -

1) Efficient HDL Coding

2) Operator Sharing

3) Functionality Sharing

4) General Circuits


1) Efficient HDL Coding:

- Try to find/research an efficient design ( Complete Domain Knowledge)

- Now develop the HDL code which accurately describes the circuit


2) Operator Sharing:

- Arithmetic operators might result large in area implementation

- Synthesis tool offers limited optimization

- Better optimization can be achieved in RTL level coding by means of Operator Sharing and Functionality Sharing

- Example:

A)


if(<condition>)

begin

r <= a+b;

end

else begin

r <= a+c;

end



- Above circuit consumes 2 Adders and 1 Mux

- Delay = max(Tadder, T boolean) + T mux


Modified RTL Code:

if(<condition>)
begin
src0 <= b;
end
else begin
src0 <= c;
end
assign r <= a + src0;




- Above circuit consumes 1 Adder and 1 Mux

- Delay = Tadder + T boolean + T mux



B)

always @(*)
begin
if( <condition>) begin
x <= a + b;
y <= 'b0;
end
else begin
x <= 'b1;
y <= c + d;
end




- Above circuit consumes 2 adders and 2 Muxes

- Delay = max(Tadder, Tboolean) + Tmux


Modified RTL code:

if (<condition>)
begin
src0 <= a;
src1 <= b;
x <= sum;
y <= 'b0;
end
else begin
src0 <= c;
src1 <= d;
x <= 'b1;
y <= sum;
end
assign sum <= src0 + src1;




- Above modified circuit consumes 1 adder and 2 Muxes.
- Tradeoff between 1 adder and 2 Muxes here. Now, is this sharing is worthwhile ? That depends on the cell area now (Generally adders are more complicated than Muxes)
- Delay = Tboolean + 2(T Mux) + Tadder


Note:

i) Merit of sharing depends on the complexity of the operator and the routing circuit
ii) Ideally, synthesis software should do this