Verilog HDL Examples - 2-DFF Synchronizer

Here, we will be going through Verilog HDL coding of 2-D Flip Flop Synchronizer followed by its Circuit Diagram and Yosys(A Synthesis Tool) Synthesis diagram.


2-DFF Synchronizer Circuit Diagram:



Verilog HDL Code:

// Code your design here
//Designed by VLSI Excellence
// 2-DFF Synchronizer

module dff_sync2( input clk, input rst, input d, output q_synced );
reg sync_flop1;
reg sync_flop2;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
sync_flop1 <= 1'b0;
sync_flop2 <= 1'b0;
end
else begin
sync_flop1 <= d;
sync_flop2 <= sync_flop1;
end
end
assign q_synced = sync_flop2;
endmodule

Yosys Synthesis Diagram:





Waveform:

EDA Playground Project Link: https://www.edaplayground.com/x/wzPx


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