Verilog HDL Examples - Blocking V/S Non Blocking Assignment (Hardware Realization) Part#4

Recalling Part#3 of this series, there is no difference in hardware synthesis of a Verilog HDL code with multiple one statement procedural block.

In this article, we will simulate both the designs mentioned in Part#3.

Part#3, Verilog HDL Code Using Non-Blocking Assignments -

//####################Multi-Process Verilog HDL Code Using Non-Blocking Assignments ####

// Code your design here

module dff(

input clk,

input rst,

input d,

output reg q0,q1,q2

);

always @(posedge clk)

begin

q0 <= d;

end

always @(posedge clk)

begin

q1 <= q0;

end

always @(posedge clk)

begin

q2 <= q1;

end

endmodule

Test Bench:

module dff_test;

reg clk;

reg rst;

reg d;

wire q0,q1,q2;

dff DUT(.clk(clk), .rst(rst), .d(d), .q0(q0), .q1(q1), .q2(q2));

//Generate a 10 ns Time Period Clock

always #5 clk = ~clk;

//Drive the DUT or Generate stimuli for the DUT

initial begin

// Dump waves

$dumpfile("dump.vcd");

$dumpvars(1);

clk = 0;

@(posedge clk) d = 0;

@(posedge clk) d = 1;

#100 $finish;

end

endmodule

Waveform:




As expected, the simulation waveform looks perfect as these are cascaded D Flip Flops.

Now, Lets see the simulation result with Part#3, Verilog HDL Code Using Blocking Statements

Now, Lets replace all the Non-Blocking assignments into Blocking assignments and re-synthesize the HDL Code.


// Code your design here
module dff(

input clk,

input rst,

input d,

output reg q0,q1,q2
);
always @(posedge clk)

begin

q0 = d;

end
always @(posedge clk)

begin

q1 = q0;

end
always @(posedge clk)

begin

q2 = q1;

end

endmodule


Test Bench:

module dff_test;
reg clk;
reg rst;
reg d;
wire q0,q1,q2;

dff DUT(.clk(clk), .rst(rst), .d(d), .q0(q0), .q1(q1), .q2(q2));

//Generate a 10 ns Time Period Clock
always #5 clk = ~clk;

//Drive the DUT or Generate stimuli for the DUT

initial begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1);
clk = 0;

@(posedge clk) d = 0;
@(posedge clk) d = 1;

#100 $finish;

end
endmodule


Waveform:






Yes!!! We found the issue now ( Why Blocking Assignments are not expected while modelling Sequential Circuits).

Now, Lets change the order of the procedural blocks in above HDL Code as below -


module dff(

input clk,

input rst,

input d,

output reg q0,q1,q2

);

always @(posedge clk)

begin

q2 = q1;

end

always @(posedge clk)

begin

q1 = q0;

end

always @(posedge clk)

begin

q0 = d;

end

endmodule

Test Bench:

module dff_test;
reg clk;
reg rst;
reg d;
wire q0,q1,q2;

dff DUT(.clk(clk), .rst(rst), .d(d), .q0(q0), .q1(q1), .q2(q2));

//Generate a 10 ns Time Period Clock
always #5 clk = ~clk;

//Drive the DUT or Generate stimuli for the DUT

initial begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1);
clk = 0;

@(posedge clk) d = 0;
@(posedge clk) d = 1;

#100 $finish;

end
endmodule

Waveform:




Now the simulation result is expected but in a big design we can not keep track of the order of procedural blocks.

Observations:

1) The synthesis result (Hardware Realization) of a design with multiple procedural blocks with single statement assignment is same for both Non-Blocking and Blocking Assignments.

2) The simulation result is different

3) Lets discuss the reason of these behavior in the next article Part#5


Thank You !!!