Verilog HDL Examples - Design of Gray Code Counter (For FIFO Design)

Gray Code :

- Named after Frank Gray

- Known as reflected binary code (RBC),

- Also known just as reflected binary (RB) or Gray Code

- An ordering of the binary numeral system such that two successive values differ in only one bit (binary digit)

Decimal(Base 10) Binary (Base 2) Binary Reflected/Gray (No Base)

0 0000 0000

1 0001 0001

2 0010 0011

3 0011 0010

4 0100 0110

5 0101 0111

6 0110 0101

7 0111 0100

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8 1000 1100

9 1001 1101

10 1010 1111

11 1011 1110

12 1100 1010

13 1101 1011

14 1110 1001

15 1111 1000




- The second half of the 4 bit gray code counter is the mirror image of the first half of the gray code counter with the MSB inverted

- By inverting the 2nd MSB of the second half of the 4-bit gray code will produce the 3-bit Gray code sequence in the 3 LSBs of the 4 bit Gray code

- The 3-bit Gray code with the MSB is no longer a true Gray code because when the sequence changes from 7 to 8 or 15 to 0 , two bits are changing instead of just one bit






- Below is the circuit diagram to generate n-bit and (n-1) bit Gray code counter






- This circuit assumes that the register output is a Gray Code value itself

- Top half of the above circuit diagram shows n bit Gray code while the bottom shows (n-1) bit Gray Code Logic



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