Verilog HDL Examples - Clock Pulse Generator

Here, we will go though a Pulse Generator where we will be going through its RTL implementation and Test bench simulation


Verilog HDL Code:

// Clock Pulse Generater

//Author: Gyan Chand Dhaka (M.Tech VLSI Design)

// Code your design here

module clockTick#(parameter M = 5, // generate ticks after M clock cycle

N = 3 // N bits required to count upto M i.e. 2**N >= M

)(

input clk,

input rst,

output clkPulse

);

modMCounter #(.M(M), .N(N)) clockPulse5cycle (.clk(clk), .rst(rst), .complete_tick(clkPulse));

endmodule


module modMCounter#(parameter M = 5, // count from 0 to M-1

N = 3 // N bits required to count upto M i.e. 2**N >= M

)(

input clk,

input rst,

output complete_tick,

output [N-1:0] count

);


reg [N-1:0] count_reg;

wire[N-1:0] count_next;

always @(posedge clk, posedge rst)

begin

if (rst)

count_reg <= 0;

else

count_reg <= count_next;

end

// set count_next to 0 when maximum count is reached i.e. (M-1)

// otherwise increase the count

assign count_next = (count_reg == M-1) ? 0 : count_reg + 1 ;

//Generate 'tick' on each maximum count

assign complete_tick = (count_reg == M-1) ? 1 : 0;

assign count = count_reg; // assign count to output port

endmodule


Test Bench Design:

// Code your testbench here

//Author: Gyan Chand Dhaka (M.Tech VLSI Design)

module clockPulsetest;

reg clk;

reg rst;

wire clkPulse;

// Instantiate design under test

clockTick#(16,4) clkPulseGenerator(.clk(clk), .rst(rst),

.clkPulse(clkPulse));

initial begin

clk = 0;

rst = 1;

end

always begin

#5 clk = ~clk;

end

initial begin

// Dump waves

$dumpfile("dump.vcd");

$dumpvars(1);

$display("Reset flop.");

display;

rst = 0;

end

task display;

#1 $display("clkPulse:%0h",

clkPulse);

endtask

endmodule

Waveform:



EDA Playground Project Link: https://www.edaplayground.com/x/ak9s


Thanks !!!