Static Timing Analysis - Part#7 (Timing Constraints)

Timing Constraints:

- There are two main problems which can arise in synchronous logic designs

1) Max Delay : The data does not have enough time to pass from one register to the next register before the next clock edge

- Max delay violations are the result of slow data path, including the register's Tsetup time, therefore it is often called Setup Path/Setup Constraint

- A setup constraint specifies how much time is necessary for data to to be available at the input if a sequential device before the clock edge that captures the data in the device.




2) Min Delay : The data path is so short that it passes through several registers during the same clock cycle

- Min delay violations are the result of sort data path, causing the data to change before the register's Thold time has passed, therefore it is often called the Hold Path/Hold Constraint

- A hold constraint specifies how much time is necessary for data to be stable at the input of a sequential device after the clock edge that captures the data in the device









In depth Understanding of Setup and Hold Constraints:

Setup(Max) Constraint :






1) After the clock rises, it takes tcq for the data to propagate to point A.

2) Then the data goes through the delay of the logic to get to point B

3) The data has to arrive at point B, tsetup before the next clock edge

In general, out timing path is a race –

1) Between the data arrival, starting with the launching clock edge and

2) The data capture, one clock period later










Please visit Clock Skew and Clock Jitter Concepts on how they impact the Setup Timing Constraint




Hold (Min) Constraint :





1) Hold problems occur due to the logic changing before thold has passed





2) This is not a function of a cycle time – it is relative to a single clock edge

In general,

1) The clock rises and the data at A changes after tcq

2) The data at B changes tpd(logic) later

3) Since the data at B has to stay stable for thold after the clock edge (for the second register). The change at B has to be at least thold after the clock edge











- Hold time is the amount of time that FF0’s old data must persist at the D input of FF1 after the clock edge

- Please visit Clock Skew and Clock Jitter Concepts on how they impact the Hold Timing Constraint



Summary :

1) For setup constraints, the data has to be propagate fast enough to be captured by the next clock edge.

- This sets our maximum frequency

- If we have setup failures, we can always just slow down the clock

2) For Hold constraints the data path delay has to be long enough so it is not accidently captured by the same clock edge

- This is independent of the clock period

- If there is hold failure, you can throw your chip away!!!