Verilog HDL Examples - Blocking V/S Non Blocking Assignment (Hardware Realization) Part#3

Lest see an another example in this Blocking V/S Non-Blocking Assignment Statements.

Below is the Verilog HDL Code using Non-Blocking Procedural Assignments. Later, we will see how this code gets synthesized into the hardware using Yosys Synthesis Tool.

//####################Multi-Process Verilog HDL Code Using Non-Blocking Assignments ####

// Code your design here

module dff(

input clk,

input rst,

input d,

output reg q0,q1,q2

);

always @(posedge clk)

begin

q0 <= d;

end

always @(posedge clk)

begin

q1 <= q0;

end

always @(posedge clk)

begin

q2 <= q1;

end

endmodule

Yosys Synthesis Diagram:





As expected, the Verilog HDL Code gets realized into 3 cascaded D Flip-Flops correctly.


Now, Lets replace all the Non-Blocking assignments into Blocking assignments and re-synthesize the HDL Code.

// Code your design here
module dff(

input clk,

input rst,

input d,

output reg q0,q1,q2
);
always @(posedge clk)

begin

q0 = d;

end
always @(posedge clk)

begin

q1 = q0;

end
always @(posedge clk)

begin

q2 = q1;

end

endmodule

Yosys Synthesis Diagram:






Well, there is no difference in the synthesized hardware using either Blocking or Non-Blocking statements.


Observations:

1) If there is only single line statement in the procedural block, then there is no difference in the synthesized hardware while using either Blocking or Non-Blocking assignments.


2) What about simulation results ? Lets see in the next article Part#4



Thank You !!!