Verilog HDL Examples - Blocking V/S Non Blocking Assignment (Hardware Realization) Part#2

As you see in the previous article Part#1, realization of a single D Flip Flop using both Blocking and Non Blocking Assignments are exactly same and CORRET !!! ( Realizes a correct D Flip Flop Circuit).

Now, Lets see how the HDL Code for a cascaded 2 D Flip Flop design realizes into the Hardware.

Note: As per Verilog guidelines, one must always use Non-Blocking Assignments while modelling Sequential Circuits. Lets validate this statement in this series of articles.

Here, is the Verilog HDL code for Cascaded 2 D Flip Flop Design.


//########Cascaded 2 D Flip Flop Design Using Non Blocking Assignments #############

// Code your design here

module dff(

input clk,

input rst,

input d,

output reg q0,q1

);

always @(posedge clk)

begin

if(!rst)

begin

q0 <= 1'b0;

q1 <= 1'b0;

end

else

begin

q0 <= d;

q1 <= q0;

end

end

endmodule

Yosys Synthesis Diagram for Above Design:


Yes!!! The Verilog HDL Design realizes perfectly into two cascaded D Flip Flops.


Now, Lets replace Non Blocking Assignments into Blocking Assignments and re-synthesis the design.


//############# Cascaded 2 D Flip Flop Design Using Blocking Assignments#############


// Code your design here
module dff(

input clk,

input rst,

input d,

output reg q0,q1
);

always @(posedge clk)

begin

if(!rst)

begin

q0 = 1'b0;

q1 = 1'b0;

end

else

begin

q0 = d;

q1 = q0;

end

end

endmodule

Yosys Synthesis Diagram for Above Design:




Ohh Noo!!! Its messed up. There is no second D Flip Flop realized at all from the Verilog HDL Code!!!

Now, you observe the difference in Blocking and Non Blocking Assignment statements.

Observations:

1) There is no difference while realizing a single D Flip Flop using either Blocking or Non Blocking Assignment statements.

2) When the number of flip flop increases more than 1, the circuit realization is not correct from its HDL Code.

3) The reason is Blocking assignments executes sequentially and not concurrently at a clock tick. Hence, here Q1 gets assigned a value after Q0 gets assigned and not concurrently at the posedge clk.

Lets see some more experiments on Blocking V/S Non-Blocking Assignments in the next Part#3 of this article series.

Thank You !!!