Verilog HDL Examples - Simple DFF (Synchronous and Asynchronous Variant)

Here, we will be going through Verilog HDL coding of Simple Asynchronous and Synchronous D-FF HDL Coding and their Yosys(A Synthesis Diagram) Synthesis Diagram.


Simple Asynchronous D-FF HDL Coding:

// Code your design here

//Simple DFF Example with Asynchronous Reset

module dff (

input clk,

input rst,

input d,

output reg q,

output qb

);

assign qb = ~q;

always @(posedge clk or posedge rst)

begin

if (rst) begin

// Asynchronous reset when reset goes high

q <= 1'b0;

end else begin

// Assign D to Q on positive clock edge

q <= d;

end

end

endmodule

Yosys Synthesis Diagram:

EDA Playground Project Link: https://www.edaplayground.com/x/AF6b

Simple Synchronous D-FF HDL Coding:

// Code your design here

//Simple DFF Example with Synchronous Reset

module dff (

input clk,

input rst,

input d,

output reg q,

output qb

);

assign qb = ~q;

always @(posedge clk)

begin

if (rst) begin

// Synchronous reset when reset goes high

q <= 1'b0;

end else begin

// Assign D to Q on positive clock edge

q <= d;

end

end

endmodule


Yosys Synthesis Diagram:



EDA Playground Project Link: https://www.edaplayground.com/x/SSTB




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