In the article, we will be doing Verilog HDL Coding for a simple D Flip Flop using Blocking and Non Blocking Assignments and will see how this HDL will get realize into the real D Flip Flop Circuit/Hardware.
Here, the goal is to understand the correct use of Blocking and Non Blocking assignment statements in Verilog HDL.
Believe me , this article series outcomes are going to be very interesting. This is part one of Blocking V/S Non Blocking Assignment Experiment.
Lets Start !!!
Here, is the Verilog HDL code for a simple D Flip Flop using Non Blocking Assignment Statements in the Procedural Block(Note: 'always' and 'initial' are called procedural block in Verilog HDL)
//#############D FF Verilog HDL Code with Non Blocking Assignments##################
// Code your design here
module dff(
input clk,
input rst,
input d,
output q0
);
always @(posedge clk)
begin
if(!rst)
begin
q0 <= 1'b0;
end
else
begin
q0 <= d;
end
end
endmodule
Now, Lets see how this HDL code gets realize to the hardware using Yosys Synthesis Tool.
Yosus Synthesis Diagram:
As you can see in the above diagram, the HDL code gets realized correctly into one MUX (Because of if/else condition) and one D Flip Flop as expected.
Now, Lets replace all Non- Blocking assignments into Blocking assignments in the Verilog HDL code and observe the new realized hardware by synthesis tool again.
//############ D FF Verilog HDL Code with Blocking Assignments########
// Code your design here
module dff(
input clk,
input rst,
input d,
output q0
);
always @(posedge clk)
begin
if(!rst)
begin
q0 = 1'b0;
end
else
begin
q0 = d;
end
end
endmodule
Yosys Synthesis Diagram:
As you can see in the above both diagrams, there is no difference ( They both are exactly identical).
Observations:
1) Realization of a single D Flip Flop results exactly same with Blocking as well as Non -Blocking Signal Assignments.
2) Now, are these Blocking and Non Blocking Assignments are interchangeable ? Is there any difference in using these both?
Lets discuss more on Blocking V/S Non Blocking Assignments in Part#2 of this Article Series.
Thanks You !!!
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