Verilog HDL Examples - Mod-M Counter Design with a Tick Generated

Here, we will go through a Mod- M Counter Design Verilog HDL Code as well as its Simulation and Yosys Synthesis.


Verilog HDL Code for a Mod-M Counter:

// Design of a Mod-M counter which generates a 1 clock cycyle pulse as well when count reaches to M

//Author: Gyan Chand Dhaka

// Code your design here

module modMCounter#(parameter M = 5, // count from 0 to M-1

N = 3 // N bits required to count upto M i.e. 2**N >= M

)(

input clk,

input rst,

output complete_tick,

output [N-1:0] count

);

reg [N-1:0] count_reg;

wire[N-1:0] count_next;

always @(posedge clk, posedge rst)

begin

if (rst)

count_reg <= 0;

else

count_reg <= count_next;

end

// set count_next to 0 when maximum count is reached i.e. (M-1)

// otherwise increase the count

assign count_next = (count_reg == M-1) ? 0 : count_reg + 1 ;

//Generate 'tick' on each maximum count

assign complete_tick = (count_reg == M-1) ? 1 : 0;

assign count = count_reg; // assign count to output port

endmodule


Test Bench Design:

//Author: Gyan Chand Dhaka (M.Tech VLSI Design)

// Code your testbench here

module mod_M_Counter;

reg clk;

reg rst;

wire complete_tick;

wire [2:0]count;

// Instantiate design under test

modMCounter#(5,3) mode_M_Counter(.clk(clk), .rst(rst), .complete_tick(complete_tick), .count(count));

initial begin

clk = 0;

rst = 0;

end

always begin

#5 clk = ~clk;

end

initial begin

// Dump waves

$dumpfile("dump.vcd");

$dumpvars(1);

$display("Reset flop.");

rst = 1;

$display("Release reset.");

#5 rst = 0;

display;

task display;

#1 $display("complete_tick:%0h, count:%0h",

complete_tick, count);

endtask

endmodule

Waveform:

Yosys Synthesis Diagram:

EDA Playground Project Link: https://www.edaplayground.com/x/eUX8


Thanks !!!