Static Timing Analysis - (Foundation) - Part#1

Static Timing Analysis :

- Method of validating the timing performance of a circuit by checking all the possible timing paths for violation

- STA breaks the design into timing paths and calculated delay for each signal path and checks for the violations

- How does STA fit into a design flow ? Lets have a look at below flow chart -


- STA breaks the design into timing paths as shown in below figure -









- Each STA timing paths consists of the following elements -

1) Start Point : An input port OR a register clock pin

2) Combinational Logic Network : Consists of combinational logic gates. Do not have any memory or internal state elements

3) End Point : An output port OR a register input pin

- Path#1, #2, #3, #4 are called as Data Path and their respective start point and end points are as below :

Path#1 : Start Point - Input port of design ; End Point - Data input pin of Flip-Flop/Latch

Path#2 : Start Point - Clock pin of Flip-Flop/Latch ; End Point - Data input pin of Flip/Flop/Latch

Path#3 : Start Point - Clock pin of Flip-Flop/Latch; End Point - Output port of design

Path#4 : Start Point - Input port of design; End Point - Output port of design

- Other path types which STA tool takes care while doing timing analysis are as below ( Shown in below figure)





- Clock Path : Path from a clock input pin OR cell pin to the clock pin of a sequential element

- Clock Gating Path : Path from input port to a clock gating cell used for clock Gater setup and hold check. Here EN pin is used to gate the clock, such paths are neither clock path nor data path (Does not satisfy the Data path or Clock path definition) and called as Clock Gating Path.

- Asynchronous Path : Path from an input port to an asynchronous set/reset pin of a sequential element for recovery and removal checks




- After breaking down a design into a set of timing paths, STA tool calculates the delay along each path. The total delay of the path is sum of all the cell delays and net delays in the path.

- Each combinational logic cloud might contain multiple paths from input to output as shown in below figure. STA uses longest path to calculate the maximum delay and shortest path to calculate minimum delay.




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