Wednesday, May 4, 2022

Verilog HDL Examples : Design of Simple RAM (Random Access Memory)



Here, we will go through design of a simple RAM Block , its Verilog HDL coding and Test bench Simulation.

- The RAM has only one Write and One Read Port.

Verilog HDL Code:

/ Random Access Memory (RAM) with 1 read port and 1 write port

// Code your design here

module simple_ram #(parameter DATA_WIDTH = 16,

parameter ADDRESS_WIDTH = 4,

parameter ADDRESS_MAX = 16 //2^ADDRESS_WIDTH

)(

// Reset Sigal

input rst,

//Write Port SIgnals

input wr_clk,

input [ADDRESS_WIDTH-1 :0] wr_address,

input [DATA_WIDTH-1 :0] wr_data,

input wr_enable,

//Read Port Signals

input rd_clk,

input [ADDRESS_WIDTH-1 : 0] rd_address,

output reg [DATA_WIDTH-1 :0] rd_data

);

// Memory as multi-dimensional array

reg [DATA_WIDTH-1:0] memory [ADDRESS_MAX-1:0];

integer i;

//Initialize RAM memory

always @ (rst)

begin

if(rst)

begin

for(i = 0; i < ADDRESS_MAX; i = i +1)

begin

memory[i] = 16'h0;

end

end

end

// Write data to memory

always @(posedge wr_clk) begin

if (wr_enable) begin

memory[wr_address] <= wr_data;

end

end

// Read data from memory

always @(posedge rd_clk) begin

rd_data <= memory[rd_address];

end

endmodule



Test Bench:

// Code your testbench here

// or browse Examples

module simple_ram_test;

reg rst;

reg wr_clk;

reg [4:0] wr_address;

reg [7:0] wr_data;

reg wr_enable;

reg rd_clk;

reg [4:0] rd_address;

wire [7:0] rd_data;

//Instantiate Design Under Test

simple_ram #(8, 5, 32) RAM (

.wr_clk(wr_clk),

.wr_address(wr_address),

.wr_data(wr_data),

.wr_enable(wr_enable),

.rd_clk(rd_clk),

.rd_address(rd_address),

.rd_data(rd_data));

initial begin

// Dump waves

$dumpfile("dump.vcd");

$dumpvars(1);

rst = 0;

#5 rst = 1;

#5 rst = 0;

wr_clk = 0;

rd_clk = 0;

wr_enable = 0;

rd_address = 5'hAA;

wr_address = rd_address;

$display("Read initial data.");

toggle_rd_clk;

$display("data[%0h]: %0h",

rd_address, rd_data);

$display("Write new data.");

wr_enable = 1;

wr_data = 8'hBB;

toggle_wr_clk;

wr_enable = 0;

$display("Read new data.");

toggle_rd_clk;

$display("data[%0h]: %0h",

rd_address, rd_data);

rst = 1;

#5 rst = 0;

end

task toggle_wr_clk;

begin

#10 wr_clk = ~wr_clk;

#10 wr_clk = ~wr_clk;

end

endtask

task toggle_rd_clk;

begin

#10 rd_clk = ~rd_clk;

#10 rd_clk = ~rd_clk;

end

endtask

endmodule


Simulation Waveform:







Thanks !!!

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