Static Timing Analysis - (Foundation) - Part#4

Unateness Examples : 1) Buffer : - There are two timing arcs in buffer - A) Rising input A to Y (Rising output Y) B) Falling input A to Y (Falling output Y) - Output exactly follows the input egde - Positive Unate 2) AND...

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Static Timing Analysis - (Foundation) - Part#3

Characteristics of Timing Arc : - Below information is derived from the timing library 1) Unateness 2) Delay 3) Slew 1) Unateness : - How the output (of a cell) changes for different types of transition on input - Specifies how the output is...

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Static Timing Analysis - (Foundation) - Part#2

Standard Cells : - The functionality of a chip is designed using the basic blocks of combinational logic gates (AND, OR, NAND, NOR, AOI, OAI) and sequential elements (Flip-Flops, Latches). - These blocks are predesigned and called standard cells - The timing information and functionality...

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Static Timing Analysis - (Foundation) - Part#1

Static Timing Analysis : - Method of validating the timing performance of a circuit by checking all the possible timing paths for violation - STA breaks the design into timing paths and calculated delay for each signal path and checks for the violations - How does STA fit into a design flow...

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AMBA (Advanced Microcontroller Bus Architecture) Specification - Questions & Answers Part#4

1) Explain Wrap Beat Calculation in AHB ? Answer - Following Tasks will Give Information About Wrap Boundary Beat Location Calculation // wrap4_beat_info() task wrap4_beat_info (logic [2:0] hburst,logic [31:0] haddr,logic [2:0] hsize); if(hsize==3'b010 && hburst==`AHB_WRAP4 ) begin ...

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AMBA (Advanced Microcontroller Bus Architecture) Specification - Questions & Answers Part#3

1) When a master rebuilds a burst which has been terminated early are there any limitations on how it rebuilds the burst? Answer - The only limitation is that the master uses legal burst combinations to rebuild the burst. For example, if a master was performing an 8 beat burst, but had only completed 3 transfers before losing control of the bus, then the remaining 5 transfers could be performed either...

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AMBA (Advanced Microcontroller Bus Architecture) Specification - Questions & Answers Part#2

1) Can HTRANS change whilst HREADY is low? Answer - In general, an AHB master should not change control signals whilst HREADY is low. However it is allowable to change HTRANS in the following conditions: HTRANS = IDLE The AHB master is performing internal operations and has not yet committed to a bus transfer. However during the AHB wait states (HREADY low) the master may determine that a bus transfer...

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AMBA (Advanced Microcontroller Bus Architecture) Specification - Questions & Answers Part#1

1) Does HWDATA have to remain stable during an extended transfer (when hready is low )? Answer - HWDATA is guaranteed to remain at the same value when sampled at different clock edges in an extended transfer. However, it is possible that HWDATA can glitch after clock edges, returning to the same value as previously driven. It is possible to observe this behavior when using a typical synthesis design...

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Bit Manipulation Circuit Design Using Verilog HDL

Bit Manipulation Circuit Design:Design a circuit which manipulates data available in the memory and outputs them as depicted in below diagram Solution :Assume we have 15 words of data each having 15 bits as shown in the figure above.Verilog HDL Code ://///////////////////////Bit...

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Design of Microprocessor Branch Prediction Algorithms

MICROPROCESSOR BRANCH PREDICTION ALGORITHMS Branch Prediction: - A technique used in CPU design that attempts to guess the outcomes of a conditional operation and prepare for the most likely result - The digital circuit which performs this operation is known as branch predictor - It is an important...

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MIPS Processor Design - Part#2

Micro-Processor Without Interlocked Pipelined Stages(MIPS)Introduction: MIPS (an acronym for Microprocessor without Interlocked Pipelined Stages) is a reduced instruction set computer (RISC) instruction set architecture developed by MIPS Technologies (formerly MIPS Computer Systems). MIPS...

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MIPS Processor Design - Part#1

Through this series of blogs, we will be understanding the design concepts and implementation of MIPS (Micro-Processor without Interlocked Pipelined Stages) Processor Design.Basically, we will be covering the below design concepts throughout this blog series of MIPS Processor Design - 1) Microprocessor Register Set 2) Microprocessor architecture (Register set and types of instruction...

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Cortex Mx Processor Operating System (OS) Friendly Features

The Cortex-M series of processor supports OS friendly features like, Shadowed Stack Pointer, SysTick Timer, SVC and PendSV exception. Lets discuss some key points of each of the as below - Use of Shadowed Stack Pointer: - Physically two stack pointers are there in Cortex M3/M4 processor ...

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Process Synchronization in Multi-Programming Operating System

Key Points about the Process Synchronization in Multi-Programming Operating Systems with Examples - In nutshell, we will be discussing below points throughout this blog - Ø Need of Process Synchronization (Problems with Multi Programming Systems) Ø Various Methods with Pros and Cons to resolve the Process Synchronization Problems. Ø Concepts and Applications of Semaphore. Ø Why semaphores are...

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Design of Cyclic Redundancy Code Generator Using Verilog HDL

Cyclic Redundancy Check (CRC) for SDIO Protocol Please visit SDIO Protocol here . However, the described CRC calculation algorithm in this blog is common and the concept can be used anywhere as per the design requirements to generate a 7 bit CRC value over a stream of data. The Cyclic...

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