Digital Design of Ripple Carry Adder (Circuit + Verilog HDL)

Ripple Carry Adder:

- A ripple carry adder is a digital combinational circuit that produces the arithmetic sum of two binary numbers

- A N bit ripple carry adder can be constructed using N number of full adders connecting in cascaded manner

- Carry output from each full adder connects to the carry input of next full adder in a chain


Ripple Carry Adder Block Diagram:

     

Lets assume, propagation delay of a single full adder to generate its carry out signal is 'X' ns and to generate sum output is 'Y'ns

Now, Total time taken to generate carry output for a 16 bit ripple carry adder is 16*X ns. (Carry Output of Nth Full Adder)

Total time taken to generate the sum output is 15*X + Y ns ( Sum output of Nth Full Adder)

Note: Sum output from the last full adder ( Nth Full Adder) will be generated once the carry output from (N-1)th full adder is avialble.

So, the worstcase delay of the 16 Bit Ripple Carry Adder is Max{16*X , (15*X+Y)}

 

Verilog HDL Code:

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// Code your design here
`include "full_adder.sv"
module ripple_carry_adder(a_in, b_in, carry_in, sum_o, carry_o);
  input [3:0] a_in;
  input [3:0] b_in;
  input carry_in;
  output [3:0] sum_o;
  output carry_o;
  wire carry_1, carry_2, carry_3;
  full_adder FA1(.a_in(a_in[0]), .b_in(b_in[0]), .carry_in(carry_in), .sum_o(sum_o[0]), .carry_o(carry_1));
  full_adder FA2(.a_in(a_in[1]), .b_in(b_in[1]), .carry_in(carry_1), .sum_o(sum_o[1]), .carry_o(carry_2)); 
  full_adder FA3(.a_in(a_in[2]), .b_in(b_in[2]), .carry_in(carry_2), .sum_o(sum_o[2]), .carry_o(carry_3));
  full_adder FA4(.a_in(a_in[3]), .b_in(b_in[3]), .carry_in(carry_3), .sum_o(sum_o[3]), .carry_o(carry_o));
endmodule
module full_adder (a_in, b_in, carry_in, sum_o, carry_o);
  input a_in;
  input b_in;
  input carry_in;
  output sum_o;
  output carry_o;
  assign sum_o = (a_in ^ b_in ^ carry_in);
  assign carry_o = (((a_in ^ b_in)& carry_in) | (a_in & b_in));
  //assign carry_o = ((a_in & b_in) | (b_in & carry_in) | (a_in & carry_in));  
endmodule

Test Bench Code:

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module ripple_carry_adder_test
  reg [3:0]a_in;
  reg [3:0]b_in;
  reg carry_in;
  wire [3:0]sum_o;
  wire carry_o; 
  // Instantiate design under test
  ripple_carry_adder DUT(.a_in(a_in), .b_in(b_in), .carry_in(carry_in), .sum_o(sum_o), .carry_o(carry_o));      
  initial begin
    // Dump waves
    $dumpfile("dump.vcd");
    $dumpvars(1);  
    a_in = 4'b0000;
    b_in = 4'b0000;
    carry_in = 1'b0;
    #10 a_in = 4'b0000; b_in = 4'b0001; carry_in = 1'b1;
    #10 a_in = 4'b0001; b_in = 4'b0001; carry_in = 1'b0;
    #10 a_in = 4'b0010; b_in = 4'b0011; carry_in = 1'b1;
    #10 a_in = 4'b1111; b_in = 4'b1010; carry_in = 1'b0;
    #10 a_in = 4'b1001; b_in = 1'b1000; carry_in = 1'b1;
    #10 a_in = 4'b1101; b_in = 4'b1001; carry_in = 1'b0;
    #10 a_in = 4'b0001; b_in = 4'b0011; carry_in = 1'b1;
    #10 a_in = 4'b0001; b_in = 4'b0000; carry_in = 1'b0;  
  end       
endmodule

Simulation Waveform:

    

Thanks !