Digital Design of Parallel Adder/Subtractor (Circuit + HDL Code )

Parallel Adder/Subtractor Design:

• The parallel adder/subtractor circuit is capable to perform both addition and subtraction operations
• The control input of the parallel adder/subtractor circuit defines if it is going to perfom additon or subtraction operation
• If control signal is '0' , the circuit will perform addition operation else if control input is '1' , the circuit will perform subtraction operation
• The Ex-Or Gate will invert the second input (B) bits when control input is 1, hence performing 1's compliemnt of input B
• The control input will be added with 1's compleiemnt of B using full adder (FA0) which will result in 2's compliemnt of Ba
• Finally A + 2's Compliemnt value of B , will be added , which is nothing but 'A - B'

Block Diagram of Parallel Adder/Subtractor:

    

Verilog HDL Code:

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<`include "full_adder.sv">

module parallel_adder_subtractor(
    a_in, 
    b_in, 
    control_in, 
    sum_diff_o, 
    carry_borrow_o
);

    input [3:0] a_in;
    input [3:0] b_in;
    input control_in;
    output [3:0] sum_diff_o;
    output carry_borrow_o; 

    wire [3:0] b_in_q;
    wire carry_borrow_1, carry_borrow_2, carry_borrow_3; 

    assign b_in_q = b_in ^ ({4{control_in}});

    full_adder FA1(
        .a_in(a_in[0]), 
        .b_in(b_in_q[0]), 
        .carry_in(control_in), 
        .sum_o(sum_diff_o[0]), 
        .carry_o(carry_1)
    );

    full_adder FA2(
        .a_in(a_in[1]), 
        .b_in(b_in_q[1]), 
        .carry_in(carry_1), 
        .sum_o(sum_diff_o[1]), 
        .carry_o(carry_2)
    );

    full_adder FA3(
        .a_in(a_in[2]), 
        .b_in(b_in_q[2]), 
        .carry_in(carry_2), 
        .sum_o(sum_diff_o[2]), 
        .carry_o(carry_3)
    );

    full_adder FA4(
        .a_in(a_in[3]), 
        .b_in(b_in_q[3]), 
        .carry_in(carry_3), 
        .sum_o(sum_diff_o[3]), 
        .carry_o(carry_borrow_o)
    );

endmodule


module full_adder (
    a_in, 
    b_in, 
    carry_in, 
    sum_o, 
    carry_o
);

    input a_in;
    input b_in;
    input carry_in;
    output sum_o;
    output carry_o;

    assign sum_o = (a_in ^ b_in ^ carry_in);
    assign carry_o = (((a_in ^ b_in) & carry_in) | (a_in & b_in));

    //assign carry_o = ((a_in & b_in) | (b_in & carry_in) | (a_in & carry_in));  

endmodule
    

Test Bench Code:

-------------------------------------------------------------------------------------------------------------------------

module parallel_adder_subtractor_test>

    module parallel_adder_subtractor_test;
  reg [3:0]a_in;
  reg [3:0]b_in;
  reg control_in; 
  wire [3:0]sum_diff_o;
  wire carry_borrow_o;
  // Instantiate design under test
  parallel_adder_subtractor DUT(.a_in(a_in), .b_in(b_in), .control_in(control_in), .sum_diff_o(sum_diff_o), .carry_borrow_o(carry_borrow_o));
  initial begin 
	  // Dump waves
	  $dumpfile("dump.vcd");
	  $dumpvars(1);
	  a_in = 4'b0000; 
	  b_in = 4'b0000;
	  control_in = 1'b0;
	  #10 a_in = 4'b0000;
	  b_in = 4'b0001;
	  control_in = 1'b1;
	  #10 a_in = 4'b0001;
	  b_in = 4'b0001;
	  control_in = 1'b0;
	  #10 a_in = 4'b0010;
	  b_in = 4'b0011;
	  control_in = 1'b1;
	  #10 a_in = 4'b1111;
	  b_in = 4'b1010;
	  control_in = 1'b0;
	  #10 a_in = 4'b1001;
	  b_in = 1'b1000;
	  control_in = 1'b1;
	  #10 a_in = 4'b1101;
	  b_in = 4'b1001;
	  control_in = 1'b0; 
	  #10 a_in = 4'b0001;
	  b_in = 4'b0011; 
	  control_in = 1'b1;
	  #10 a_in = 4'b0001;
	  b_in = 4'b0000; control_in = 1'b0;
  end    
 endmodule
    

Simulation Waveform:

  

Thanks !