Digital Design of Half Subtractor (Circuit + Verilog HDL)

 

Subtractor:

- A subtractor can be designed using the same approach as that of an adder

Half Sutractor:

- A combinational circuit which is used to perform subtraction of 2 bits

- The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi digit subtraction operation

Half Subtractor Block Diagram:

   

 Half Subtractor Truth Table:

a_in	b_in	diff_o	borrow_o
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

                                          Table 1 : Half Subtractor Truth Table

Circuit Design of Half Subtractor:

Logic Expression (From Table 1 Truth Table)

diff_o = a_in' . b_in + a_in . b_in';

diff_o = a_in ^ b_in;

borrow_o = a_in' . b_in;

Hence,

           

Verilog HDL Code:

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module half_subtractor(a_in , b_in , diff_o, borrow_o);

  input a_in;

  input b_in;

  output diff_o;

  output borrow_o; 

  assign diff_o = (a_in ^ b_in);

  assign borrow_o = (~a_in & b_in);  

endmodule

Test Bench Code:

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module half_subtractor_test;

  reg a_in;

  reg b_in;

  wire diff_o;

  wire borrow_o;

  // Instantiate design under test

  half_subtractor DUT(.a_in(a_in), .b_in(b_in), .diff_o(diff_o), .borrow_o(borrow_o));      

  initial begin

    // Dump waves

    $dumpfile("dump.vcd");

    $dumpvars(1); 

    a_in = 1'b0;

    b_in = 1'b0;

    #10 a_in = 1'b1; b_in = 1'b0;

    #10 a_in = 1'b0; b_in = 1'b1; 

    #10 a_in = 1'b1; b_in = 1'b1;  

    #10 a_in = 1'b0; b_in = 1'b0;   

  end     

endmodule

Simulation Waveform:

  

Thanks !