Digital Design of 1-Bit Magnitude Comparator Type#2 (Circuit + Verilog HDL Code)

Magnitude Comparator:

- A magnitude comparator is a combinational circuit which is used to compare two binary numbers in order to find out whether one number is equal or greater or less than the other number

Block Diagram of 1 Bit Magnitude Comparator:

   

Truth Table:

          

a_in	b_in	agb_in	aeqb_in	alb_in	agb_o	aeqb_o	alb_o
0	0	X	0	X	agb_in	aeqb_in	alb_in
0	1	X	0	X	agb_in	aeqb_in	alb_in
1	0	x	0	X	agb_in	aeqb_in	alb_in
1	1	X	0	X	agb_in	aeqb_in	alb_in
0	0	X	1	X	0	1	0
0	1	X	1	X	0	0	1
1	0	X	1	X	1	0	0
1	1	x	1	x	0	1	0

 

Logic Expresison:

- From the truth table above we can see that when aeqb_in == 0, The outputs (aeqb_o, agb_o, alb_o) always gets the input values (aeqb_in, agb_in, alb_in)

- When the aeqb_in is 1, the output values are similar to one bit magnitude comparator.

- Putting in a logical expression format -

aeqb_o = (aeqb_in == 0) ? aeqb_in : (a_in' . b_in' + a_in . b_in);

agb_o = (aeqb_in == 0) ? agb_in : (a_in . b_in');

alb_o = (aeqb_in == 0) ? alb_in : (a_in' . b_in);


Circuit Diagram:

   

Verilog HDL Code:

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module magnitude_comparator_1_bit_type2(a_in, b_in, aeqb_o, agb_o, alb_o, aeqb_in, agb_in, alb_in);

  input a_in;

  input b_in;

  output aeqb_o;

  output agb_o;

  output alb_o;

  input aeqb_in;

  input agb_in;

  input alb_in;

  

 /* a_in      b_in    aeqb     agb    alb

    0        0       1        0      0

    0        1       0        0      1

    1        0       0        1      0

    1        1       1        0      0        */  

  

 reg aeqb_w, agb_w, alb_w;

  always @(*)

    begin

      if(aeqb_in)

        begin

          aeqb_w = ((~a_in & ~b_in) | (a_in & b_in));

           agb_w = (a_in & ~b_in);

           alb_w = (~a_in & b_in);

        end

      else

        begin

          aeqb_w = aeqb_in;

           agb_w = agb_in;

           alb_w = alb_in;

        end

    end

 assign aeqb_o = aeqb_w;

 assign agb_o = agb_w; 

 assign alb_o = alb_w; 

endmodule

Test Bench Code:

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module magnitude_comparator_1_bit_type2_test;

  reg a_in;

  reg b_in;

  reg aeqb_in;

  reg agb_in;

  reg alb_in;

  wire aeqb_o;

  wire agb_o;

  wire alb_o;

  // Instantiate design under test

  magnitude_comparator_1_bit_type2 DUT(.a_in(a_in), .b_in(b_in), .aeqb_in(aeqb_in), .agb_in(agb_in), .alb_in(alb_in), .aeqb_o(aeqb_o), .agb_o(agb_o), .alb_o(alb_o));     

  initial begin

    // Dump waves

    $dumpfile("dump.vcd");

    $dumpvars(1); 

    a_in = 1'b0;

    b_in = 1'b0;

    aeqb_in = 1'b0;

    agb_in = 1'b0;

    alb_in = 1'b0;

    #10 a_in = 1'b1; b_in = 1'b0;

    #10 a_in = 1'b0; b_in = 1'b1;

    #10 a_in = 1'b1; b_in = 1'b1;

    #10 a_in = 1'b0; b_in = 1'b0; 

    #5 aeqb_in = 1'b1;

    #10 a_in = 1'b1; b_in = 1'b0;

    #10 a_in = 1'b0; b_in = 1'b1;

    #10 a_in = 1'b1; b_in = 1'b1; 

    #10 a_in = 1'b0; b_in = 1'b0; 

  end

endmodule

Simulation Waveform:

   

Thanks !