Digital Design of 1-Bit Magnitude Comparator Type#1 (Circuit + Verilog HDL Code)

Magnitude Comparator:

- A magnitude comparator is a combinational circuit which is used to compare two binary numbers in order to find out whether one number is equal or greater or less than the other number

Block Diagram of 1 Bit Magnitude Comparator:

  

Truth Table of 1 Bit Magnitude Comparator:      

a_in	b_in	a_in > b_in	a_in = b_in	a_in < b_in
0	0	0	1	0
0	1	0	0	1
1	0	1	0	0
1	1	0	1	0

                        
                                Table 1 : 1 Bit Magnitude Comaparator Truth Table

Logic Expression ( From the Truth Table 1 Above):

Lets call a_in > b_in as agb, a_in = b_n as aeq, a_in < b_in as alb

From the truth table :

agb = a_in . b_in';

        aeqb = a_in' . b_in + a_in . b_in' ;

        aeqb = a_in ^ b_in;

        alb = a_in . b_in' ;

Circuit Diagram of 1 Bit Magnitude Caomapartor:

   

    

Verilog HDL Code:

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module magnitude_comparator_1_bit

module magnitude_comparator_1_bit(
    a_in, 
    b_in, 
    aeqb_o, 
    agb_o, 
    alb_o
);

    input a_in;
    input b_in;
    output aeqb_o;
    output agb_o;
    output alb_o;

    /* 
    a_in      b_in    aeqb     agb    alb
    0        0       1        0      0
    0        1       0        0      1
    1        0       0        1      0
    1        1       1        0      0
    */  

    assign aeqb_o = ((~a_in & ~b_in) | (a_in & b_in));
    assign agb_o = (a_in & ~b_in);
    assign alb_o = (~a_in & b_in);

endmodule
    

Test Bench Code:

-----------------------------------------------------------------------------------------------------------------------

module magnitude_comparator_1_bit_test

module magnitude_comparator_1_bit_test;

    reg a_in;
    reg b_in;
    wire aeqb_o;
    wire agb_o;
    wire alb_o;

    // Instantiate design under test
    magnitude_comparator_1_bit DUT(
        .a_in(a_in), 
        .b_in(b_in), 
        .aeqb_o(aeqb_o), 
        .agb_o(agb_o), 
        .alb_o(alb_o)
    );

    initial begin
        // Dump waves
        $dumpfile("dump.vcd");
        $dumpvars(1);

        a_in = 1'b0;
        b_in = 1'b0;

        #10 a_in = 1'b1; b_in = 1'b0;
        #10 a_in = 1'b0; b_in = 1'b1;
        #10 a_in = 1'b1; b_in = 1'b1; 
        #10 a_in = 1'b0; b_in = 1'b0;  
    end     

endmodule
    

Simulation Waveform:

Thanks !